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* Clean up some unnecessary mutex guards.Zachary Turner2014-06-162-29/+28
| | | | | | | | | | | | | | | These were being used as unreferenced parameters to enforce that the methods must not be called without holding a mutex, but all of the methods in question were internal, and the methods were only exposed through an interface whose entire purpose was to serialize access to these structures, so expecting the methods to be accessed under a mutex is reasonable enough. Reviewed by: blaikie Differential Revision: http://reviews.llvm.org/D4162 llvm-svn: 211054
* Improve comments for r211040Louis Gerbarg2014-06-162-3/+6
| | | | | | | | Added comment to clarify why we r211040 choose to bail out of fast isel instead of generating a more complicated relocation, and fix mislabelled register in the comments of the asan test case. llvm-svn: 211052
* Revert "lit: warn when passed invalid pathname" (r210597)Hans Wennborg2014-06-161-5/+3
| | | | | | | | | It was pointed out that this breaks the "virtual test discovery" mechanism, which allows for narming tests in the test exec root. Reverting until I can figure out how to fix this. llvm-svn: 211048
* ARM: implement correct atomic operations on v7MTim Northover2014-06-162-8/+73
| | | | | | | | | | ARM v7M has ldrex/strex but not ldrexd/strexd. This means 32-bit operations should work as normal, but 64-bit ones are almost certainly doomed. Patch by Phoebe Buckheister. llvm-svn: 211042
* Fix illegal relocations in X86FastISelLouis Gerbarg2014-06-163-3/+31
| | | | | | | | | | | | On x86_86 the lea instruction can only use a 32 bit immediate value. When the code is compiled statically the RIP register is not used, meaning the immediate is all that can be used for the relocation, which is not sufficient in the case of targets more than +/- 2GB away. This patch bails out of fast isel in those cases and reverts to DAG which does the right thing. Test case included. llvm-svn: 211040
* LowerSwitch: track bounding range for the condition tree.Jim Grosbach2014-06-164-102/+209
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When LowerSwitch transforms a switch instruction into a tree of ifs it is actually performing a binary search into the various case ranges, to see if the current value falls into one cases range of values. So, if we have a program with something like this: switch (a) { case 0: do0(); break; case 1: do1(); break; case 2: do2(); break; default: break; } the code produced is something like this: if (a < 1) { if (a == 0) { do0(); } } else { if (a < 2) { if (a == 1) { do1(); } } else { if (a == 2) { do2(); } } } This code is inefficient because the check (a == 1) to execute do1() is not needed. The reason is that because we already checked that (a >= 1) initially by checking that also (a < 2) we basically already inferred that (a == 1) without the need of an extra basic block spawned to check if actually (a == 1). The patch addresses this problem by keeping track of already checked bounds in the LowerSwitch algorithm, so that when the time arrives to produce a Leaf Block that checks the equality with the case value / range the algorithm can decide if that block is really needed depending on the already checked bounds . For example, the above with "a = 1" would work like this: the bounds start as LB: NONE , UB: NONE as (a < 1) is emitted the bounds for the else path become LB: 1 UB: NONE. This happens because by failing the test (a < 1) we know that the value "a" cannot be smaller than 1 if we enter the else branch. After the emitting the check (a < 2) the bounds in the if branch become LB: 1 UB: 1. This is because by checking that "a" is smaller than 2 then the upper bound becomes 2 - 1 = 1. When it is time to emit the leaf block for "case 1:" we notice that 1 can be squeezed exactly in between the LB and UB, which means that if we arrived to that block there is no need to emit a block that checks if (a == 1). Patch by: Marcello Maggioni <hayarms@gmail.com> llvm-svn: 211038
* Refactor the disabling of Thumb-1 LDM/STM generationJames Molloy2014-06-162-7/+7
| | | | | | | | Originally I switched the LD/ST optimizer off in TargetMachine as it was previously, but Eric has suggested he'd prefer that it be short-circuited in the pass itself. No functionality change. llvm-svn: 211037
* Fix pr17056.Rafael Espindola2014-06-163-5/+11
| | | | | | | | | | | | | This makes llvm-nm ignore members that are not sufficiently aligned for lib/Object to handle. These archives are invalid. GNU AR is able to handle this, but in general just warns about broken archive members. We should probably start warning too, but for now just make sure llvm-nm exits with an 0. llvm-svn: 211036
* Convert the Archive API to use ErrorOr.Rafael Espindola2014-06-168-93/+88
| | | | | | | | | Now that we have c++11, even things like ErrorOr<std::unique_ptr<...>> are easy to use. No intended functionality change. llvm-svn: 211033
* [AArch64] Remove dead code.Tilmann Scheller2014-06-161-3/+0
| | | | | | Both function declarations lack a callee and an implementation. llvm-svn: 211029
* Hook up vector int_ctlz for AVX512.Cameron McInally2014-06-163-0/+32
| | | | llvm-svn: 211024
* [mips][mips64r6] ssnop is deprecated on MIPS32r6/MIPS64r6Daniel Sanders2014-06-164-3/+22
| | | | | | | | | | | | Summary: Depends on D4120 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: zoran.jovanovic, vmedic Differential Revision: http://reviews.llvm.org/D4121 llvm-svn: 211021
* [mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6Daniel Sanders2014-06-1617-60/+223
| | | | | | | | | | | | | | | | | Summary: There is no change to the restrictions, just the result register is stored once in the encoding rather than twice. The rt field is zero in MIPS32r6/MIPS64r6. Depends on D4119 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4120 llvm-svn: 211019
* [mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.Daniel Sanders2014-06-1623-82/+306
| | | | | | | | | | | | | | | | | | | | | Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
* Support/ConvertUTF: restore compatibility with MSVC, which only implements C89Dmitri Gribenko2014-06-161-5/+7
| | | | llvm-svn: 211016
* Support/ConvertUTF: implement U+FFFD insertion according to the recommendationDmitri Gribenko2014-06-163-9/+1342
| | | | | | | | | given in the Unicode spec That is, replace every maximal subpart of an ill-formed subsequence with one U+FFFD. llvm-svn: 211015
* [AArch64] Fix a fencepost error in lowering for llvm.aarch64.neon.uqshl.James Molloy2014-06-162-1/+10
| | | | | | Patch by Jiangning Liu! llvm-svn: 211014
* [mips] Merge most of the big/little endian checks in atomic.llDaniel Sanders2014-06-161-333/+179
| | | | | | | | | | | | | | | | | Summary: There is very little difference between the big and little endian cases in test/CodeGen/Mips/atomic.ll. Merge them together using multiple FileCheck prefixes. Depends on D4117 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4118 llvm-svn: 211013
* [mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates ↵Daniel Sanders2014-06-1618-47/+140
| | | | | | | | | | | | | | | | | | | | | rather than 16-bit in MIPS32r6/MIPS64r6 Summary: The error message for the invalid.s cases isn't very helpful. It happens because there is an instruction with a wider immediate that would have matched if the NotMips32r6 predicate were true. I have some WIP to improve the message but it affects most error messages for removed/re-encoded instructions on MIPS32r6/MIPS64r6 and should therefore be a separate commit. Depens on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4117 llvm-svn: 211012
* ARMEB: Fix trunc store for vector typesChristian Pirker2014-06-162-1/+28
| | | | | | Reviewed at http://reviews.llvm.org/D4135 llvm-svn: 211010
* Canonicalize addrspacecast ConstExpr between different pointer typesJingyue Wu2014-06-157-9/+37
| | | | | | | | | | | | | | | | | | As a follow-up to r210375 which canonicalizes addrspacecast instructions, this patch canonicalizes addrspacecast constant expressions. Given clang uses ConstantExpr::getAddrSpaceCast to emit addrspacecast cosntant expressions, this patch is also a step towards having the frontend emit canonicalized addrspacecasts. Piggyback a minor refactor in InstCombineCasts.cpp Update three affected tests in addrspacecast-alias.ll, access-non-generic.ll and constant-fold-gep.ll and added one new test in constant-fold-address-space-pointer.ll llvm-svn: 211004
* Fix copy paste errorMatt Arsenault2014-06-151-1/+1
| | | | llvm-svn: 211003
* R600: Add a rotr testcase I forgot to addMatt Arsenault2014-06-151-0/+58
| | | | llvm-svn: 211002
* R600: Remove a few more things from AMDILISelLoweringMatt Arsenault2014-06-153-27/+71
| | | | | | | Try to keep all the setOperationActions for integer ops together. llvm-svn: 211001
* R600: Fix assert on vector sdivMatt Arsenault2014-06-152-4/+36
| | | | llvm-svn: 211000
* R600: Move / cleanup more leftover AMDIL stuff.Matt Arsenault2014-06-153-71/+30
| | | | llvm-svn: 210998
* R600: Move division custom lowering out of AMDILISelLoweringMatt Arsenault2014-06-153-271/+257
| | | | llvm-svn: 210997
* Temporarily revert r210953 in an attempt to bring the ARM buildbotsEric Christopher2014-06-159-26/+24
| | | | | | back. llvm-svn: 210996
* R600: Report that integer division is expensive.Matt Arsenault2014-06-152-4/+61
| | | | | | Divides by weird constants now emit much better code. llvm-svn: 210995
* R600: Remove dead codeMatt Arsenault2014-06-152-75/+11
| | | | llvm-svn: 210994
* PR20038: DebugInfo missing DIEs for some concrete variables.David Blaikie2014-06-152-0/+149
| | | | | | | | I haven't nailed this down entirely, but this is about as small of a test case as I can seem to construct and adequately demonstrates the crasher. I'll continue investigating the root cause/fix(es). llvm-svn: 210993
* Add specialization of FoldingSetTrait for std::pair.Manuel Klimek2014-06-151-0/+8
| | | | llvm-svn: 210990
* LegalizeDAG: make sure cast is unsigned before using FP_TO_UINT.Tim Northover2014-06-151-1/+4
| | | | | | | | | | | | It's valid to use FP_TO_SINT when asking for a smaller type (e.g. all "unsigned int16" values fit into a "signed int32"), but the reverse isn't true. Unfortunately, I'm not actually aware of any architecture with asymmetric FP_TO_SINT and FP_TO_UINT handling and the logic happens to work in the symmetric case, so I can't actually write a test for this. llvm-svn: 210986
* AArch64: improve handling & modelling of FP_TO_XINT nodes.Tim Northover2014-06-153-30/+162
| | | | | | | | There's probably no acatual change in behaviour here, just updating the LowerFP_TO_INT function to be more similar to the reverse implementation and updating costs to current CodeGen. llvm-svn: 210985
* AArch64: improve vector [su]itofp handling.Tim Northover2014-06-155-65/+210
| | | | | | | This somehow got missed in the AArch64 merge, so should fix a performance regression since 3.4. llvm-svn: 210984
* Don't expect tests always crashing. Add "REQUIRES:asserts".NAKAMURA Takumi2014-06-152-0/+2
| | | | llvm-svn: 210983
* Replacing the private implementations of SwapValue with calls to ↵Artyom Skrobov2014-06-142-130/+120
| | | | | | sys::swapByteOrder() llvm-svn: 210980
* Using llvm::sys::swapByteOrder() for the common case of byte-swapping a ↵Artyom Skrobov2014-06-145-8/+8
| | | | | | value in place llvm-svn: 210978
* Adding llvm::sys::swapByteOrder() for the common use-case of byte-swapping a ↵Artyom Skrobov2014-06-142-0/+53
| | | | | | value in place llvm-svn: 210976
* Renaming SwapByteOrder() to getSwappedBytes()Artyom Skrobov2014-06-1411-55/+55
| | | | | | The next commit will add swapByteOrder(), acting in-place llvm-svn: 210973
* R600: Add failing testcases.Matt Arsenault2014-06-142-0/+28
| | | | | | | These are reduced from assert in the OpenCV CvtColor8u.BGR5652GRAY test. llvm-svn: 210969
* Fix typoMatt Arsenault2014-06-141-1/+1
| | | | llvm-svn: 210968
* R600: Fix asserts related to constant initializersMatt Arsenault2014-06-142-5/+40
| | | | | | | | | | | This would assert if a constant address space was extern and therefore didn't have an initializer. If the initializer was undef, it would hit the unreachable unhandled initializer case. An extern global should never really occur since we don't have machine linking, but bugpoint likes to remove initializers. llvm-svn: 210967
* R600: Use address space enum instead of valueMatt Arsenault2014-06-141-6/+7
| | | | llvm-svn: 210966
* Remove extra whitespace in function declaration. No functionality change.Nick Lewycky2014-06-141-2/+2
| | | | llvm-svn: 210965
* DebugInfo: Remove some extra handling of abstract variables and instead rely ↵David Blaikie2014-06-132-40/+34
| | | | | | | | | | | | | | | solely on the delayed handling introduced in r210946 Now that we handle finding abstract variables at the end of the module, remove the upfront handling and just ensure the abstract variable is built when necessary. In theory we could have a split implementation, where inlined variables are immediately constructed referencing the abstract definition, and concrete variables are delayed - but let's go with one solution for now unless there's a reason not to. llvm-svn: 210961
* Remove InstrItineraryData off of the TargetMachine - it's alreadyEric Christopher2014-06-132-6/+2
| | | | | | on the subtarget and just forward the accessor. llvm-svn: 210955
* Move ARMJITInfo off of the TargetMachine and down onto the subtarget.Eric Christopher2014-06-139-21/+25
| | | | | | This required untangling a mess of headers that included around. llvm-svn: 210953
* Move GlobalMerge from Transform to CodeGen.Jiangning Liu2014-06-1316-157/+152
| | | | | | | | | | This patch is to move GlobalMerge pass from Transform/Scalar to CodeGen, because GlobalMerge depends on TargetMachine. In the mean time, the macro INITIALIZE_TM_PASS is also moved to CodeGen/Passes.h. With this fix we can avoid making libScalarOpts depend on libCodeGen. llvm-svn: 210951
* The hazard recognizer only needs a subtarget, not a target machineEric Christopher2014-06-138-17/+23
| | | | | | so make it take one. Fix up all users accordingly. llvm-svn: 210948
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