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* Restrict FindBetterChain DAG combines to unindexed nodesHal Finkel2014-01-241-2/+2
| | | | | | | | | | | | These transformations obviously won't work for indexed (pre/post-inc) loads and stores. In practice, I'm not sure there is any benefit to enabling them for indexed nodes because other transformations that these might enable likely also won't handle indexed nodes. I don't have an in-tree test case that hits this problem, but an upcoming bug fix will make it much more likely. llvm-svn: 200023
* Add Constant Hoisting PassJuergen Ributzka2014-01-2420-40/+701
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pass identifies expensive constants to hoist and coalesces them to better prepare it for SelectionDAG-based code generation. This works around the limitations of the basic-block-at-a-time approach. First it scans all instructions for integer constants and calculates its cost. If the constant can be folded into the instruction (the cost is TCC_Free) or the cost is just a simple operation (TCC_BASIC), then we don't consider it expensive and leave it alone. This is the default behavior and the default implementation of getIntImmCost will always return TCC_Free. If the cost is more than TCC_BASIC, then the integer constant can't be folded into the instruction and it might be beneficial to hoist the constant. Similar constants are coalesced to reduce register pressure and materialization code. When a constant is hoisted, it is also hidden behind a bitcast to force it to be live-out of the basic block. Otherwise the constant would be just duplicated and each basic block would have its own copy in the SelectionDAG. The SelectionDAG recognizes such constants as opaque and doesn't perform certain transformations on them, which would create a new expensive constant. This optimization is only applied to integer constants in instructions and simple (this means not nested) constant cast experessions. For example: %0 = load i64* inttoptr (i64 big_constant to i64*) Reviewed by Eric llvm-svn: 200022
* Add final and owerride keywords to TargetTransformInfo's subclasses.Juergen Ributzka2014-01-247-126/+143
| | | | llvm-svn: 200021
* Doxify commentsJuergen Ributzka2014-01-241-23/+21
| | | | llvm-svn: 200020
* Fix known typosAlp Toker2014-01-24111-232/+233
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
* Report lli remote IO errors consistentlyAlp Toker2014-01-245-41/+30
| | | | | | | | | This enables IO error reports in both the child and server processes. The scheme still isn't entirely satisfactory and output is jumbled but it beats having no output at all. This will hopefully unblock ARM support (PR18057). llvm-svn: 200017
* InstSimplify: Make shift, select and GEP simplifications vector-aware.Benjamin Kramer2014-01-244-19/+114
| | | | llvm-svn: 200016
* Unify duplicated functions.Rafael Espindola2014-01-243-21/+5
| | | | llvm-svn: 200014
* Don't use "llc -filetype=obj" now that the codepath is the same.Rafael Espindola2014-01-243-3/+3
| | | | | | | r200011 remove the special codepaths in MC for inline asm, so we can now test all the logic with just llc + llvm-mc. llvm-svn: 200013
* Move emitInlineAsmEnd to the AsmPrinter interface.Rafael Espindola2014-01-246-41/+34
| | | | | | | | There is no inline asm in a .s file. Therefore, there should be no logic to handle it in the streamer. Inline asm only exists in bitcode files, so the logic can live in the (long misnamed) AsmPrinter class. llvm-svn: 200011
* DWARFContext: Fix possible memory leak since r198908.NAKAMURA Takumi2014-01-241-0/+1
| | | | llvm-svn: 200000
* llvm/projects/CMakeLists.txt: Add dragonegg.NAKAMURA Takumi2014-01-241-0/+3
| | | | llvm-svn: 199995
* Revert "Use DW_AT_high_pc and DW_AT_low_pc for the high and low pc for a"Eric Christopher2014-01-246-46/+17
| | | | | | | | in order to fix the cygwin/mingw bots. This reverts commit r199990. llvm-svn: 199991
* Use DW_AT_high_pc and DW_AT_low_pc for the high and low pc for aEric Christopher2014-01-246-17/+46
| | | | | | | | compile unit. Make these relocations on the platforms that need relocations and add a routine to ensure that we don't put the addresses in an offset table for split dwarf. llvm-svn: 199990
* [AArch64 NEON] Fix a bug in implementing register copy bwtween FPR16.Kevin Qin2014-01-242-3/+14
| | | | llvm-svn: 199978
* [SparcV9] Add support for JIT in Sparc64.Venkatraman Govindaraju2014-01-245-45/+189
| | | | | | With this change, all supported tests in test/ExecutionEngine pass in sparcv9. llvm-svn: 199977
* [X86] Prevent the creation of redundant ops for sadd and ssub with overflow.Juergen Ributzka2014-01-242-2/+51
| | | | | | | | | | | | | This commit teaches the X86 backend to create the same X86 instructions when it lowers an sadd/ssub with overflow intrinsic and a conditional branch that uses that overflow result. This allows SelectionDAG to recognize and remove one of the redundant operations. This fixes <rdar://problem/15874016> and <rdar://problem/15661073>. Reviewed by Nadav llvm-svn: 199976
* Implement atomicrmw operations in 32 and 64 bits for SPARCv9.Jakob Stoklund Olesen2014-01-244-13/+262
| | | | | | These all use the compare-and-swap CASA/CASXA instructions. llvm-svn: 199975
* [Sparc] Correct quad register list in the asm parser.Venkatraman Govindaraju2014-01-243-1/+13
| | | | | | Add test cases to check parsing of v9 double registers and their aliased quad registers. llvm-svn: 199974
* Add constants for optional header magic field.Rui Ueyama2014-01-241-0/+5
| | | | llvm-svn: 199972
* Simplify the logic for deciding when to initialize the sections.Rafael Espindola2014-01-248-24/+17
| | | | llvm-svn: 199971
* Most streamers' InitSections just create a text section. Make that the defaultRafael Espindola2014-01-247-21/+6
| | | | llvm-svn: 199969
* Use the actual .text section, it is less code than building a dummy one.Rafael Espindola2014-01-241-25/+4
| | | | llvm-svn: 199968
* Inline trivial functions called only once or twice.Rafael Espindola2014-01-241-32/+14
| | | | llvm-svn: 199967
* [LPM] Fix a logic error in LICM spotted by inspection.Chandler Carruth2014-01-241-1/+1
| | | | | | | | | | | | We completely skipped promotion in LICM if the loop has a preheader or dedicated exits, but not *both*. We hoist if there is a preheader, and sink if there are dedicated exits, but either hoisting or sinking can move loop invariant code out of the loop! I have no idea if this has a practical consequence. If anyone has ideas for a test case, let me know. llvm-svn: 199966
* Inline functions that are only called once.Rafael Espindola2014-01-242-21/+8
| | | | llvm-svn: 199965
* [cleanup] Use the type-based preservation method rather than a stringChandler Carruth2014-01-241-1/+2
| | | | | | | literal that bakes a pass name and forces parsing it in the pass manager. llvm-svn: 199963
* InitToTextSection is redundant with InitSections. Remove it.Rafael Espindola2014-01-2311-33/+2
| | | | llvm-svn: 199955
* Make the use of DW_AT_ranges in the compile unit depend also uponEric Christopher2014-01-232-5/+104
| | | | | | the existence of comdat/special sections. llvm-svn: 199954
* Remove duplicated info on what .text, .data and .bss look like.Rafael Espindola2014-01-235-45/+15
| | | | llvm-svn: 199951
* Update the X86 assembler for .intel_syntax to produce an error for invalid baseKevin Enderby2014-01-232-32/+55
| | | | | | | | | registers in memory addresses that do not match the index register. As it does for .att_syntax. rdar://15887380 llvm-svn: 199948
* lli: Factor portable messaging into a new RPCChannel facilityAlp Toker2014-01-239-168/+151
| | | | | | | The client and server now use a single unified low-level RPC core built around LLVM's existing cross-platform abstractions. llvm-svn: 199947
* Update the X86 assembler for .intel_syntax to produce an error for invalidKevin Enderby2014-01-232-3/+22
| | | | | | | | | | | scale factors in memory addresses. As it does for .att_syntax. It was producing: Assertion failed: (((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) && "Invalid scale!"), function CreateMem, file /Volumes/SandBox/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp, line 1133. rdar://14967214 llvm-svn: 199942
* Fix out of bounds access to the double regs array. Given theEric Christopher2014-01-231-1/+1
| | | | | | | code this looks correct, but could use review. The previous was definitely not correct. llvm-svn: 199940
* Add a few missing cases from r199933. Testcase coming shortly.Lang Hames2014-01-231-0/+8
| | | | llvm-svn: 199938
* Updating the getting started guide for Visual Studio a smidge.Aaron Ballman2014-01-231-8/+4
| | | | llvm-svn: 199934
* Replace vfmaddxx213 instructions with their 231-type equivalents in accumulatorLang Hames2014-01-234-3/+122
| | | | | | | loops. Writing back to the accumulator (231-type) allows the coalescer to eliminate an extra copy. llvm-svn: 199933
* Note the PR number.Rafael Espindola2014-01-231-0/+1
| | | | llvm-svn: 199932
* Remove unused include following r199929Alp Toker2014-01-231-1/+0
| | | | llvm-svn: 199930
* Replace the interim lli build fix with something cleanerAlp Toker2014-01-235-45/+15
| | | | | | | | | | Eliminates the LLI_BUILDING_CHILD build hack from r199885. Also add a FIXME to remove code that tricks the tests into passing when the feature fails to work. Please don't do stuff like this, the tests exist for a reason! llvm-svn: 199929
* [Thumbv8] Fix the value of BLXOperandIndex of isV8EligibleForITWeiming Zhao2014-01-234-7/+26
| | | | | | | | | Originally, BLX was passed as operand #0 in MachineInstr and as operand #2 in MCInst. But now, it's operand #2 in both cases. This patch also removes unnecessary FileCheck in the test case added by r199127. llvm-svn: 199928
* Move test to x86 directory.Eric Christopher2014-01-231-0/+0
| | | | llvm-svn: 199927
* Add target analysis passes to the codegen pipeline for MCJIT.Juergen Ributzka2014-01-2310-4/+30
| | | | | | | | | | | This patch adds the target analysis passes (usually TargetTransformInfo) to the codgen pipeline. We also expose now the AddAnalysisPasses method through the C API, because the optimizer passes would also benefit from better target-specific cost models. Reviewed by Andrew Kaylor llvm-svn: 199926
* [AArch64] Added vselect patterns with float and double typesAna Pazos2014-01-232-0/+17
| | | | llvm-svn: 199925
* Avoid emitting a DWARF type attribute for an ObjC property of typeEric Christopher2014-01-232-1/+106
| | | | | | | | void. Patch by Scott Talbot. llvm-svn: 199924
* Suppress an annoying "unused variable" warning caused by bug 17897.Rui Ueyama2014-01-231-0/+1
| | | | | | | | Clang says that "flow" is unused when building LLD. This patch suppresses it. Differential Revision: http://llvm-reviews.chandlerc.com/D2573 llvm-svn: 199922
* R600: Remove successive JUMP in AnalyzeBranch when AllowModify is trueTom Stellard2014-01-231-1/+7
| | | | | | | | | | | | This fixes a crash in the OpenCV OpenCL test suite. There is no lit test for this, because the test would be very large and could easily be invalidated by changes to the scheduler or other parts of the compiler. Patch by: Vincent Lejeune llvm-svn: 199919
* R600: Disable the BFE patternTom Stellard2014-01-233-1/+12
| | | | | | | | | | This pattern uses an SDNodeXForm, which isn't being emitted for some reason. I can get it to work by attaching the PatLeaf that has the XForm to the argument in the output pattern, but this results in an immediate being used in a register operand, which the backend can't handle yet. llvm-svn: 199918
* R600: Correctly handle vertex fetch clauses the precede ENDIFsTom Stellard2014-01-232-0/+30
| | | | | | | | The control flow finalizer would sometimes use an ALU_POP_AFTER instruction before the vetex fetch clause instead of using a POP instruction after it. llvm-svn: 199917
* R600: Unconditionally unroll loops that contain GEPs with alloca pointersTom Stellard2014-01-232-0/+66
| | | | | | | | | | | | Implement the getUnrollingPreferences() function for AMDGPUTargetTransformInfo so that loops that do address calculations on pointers derived from alloca are unconditionally unrolled. Unrolling these loops makes it more likely that SROA will be able to eliminate the allocas, which is a big win for R600 since memory allocated by alloca (private memory) is really slow. llvm-svn: 199916
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