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| author | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-01-24 05:24:01 +0000 |
|---|---|---|
| committer | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-01-24 05:24:01 +0000 |
| commit | 98aa7fab7edf836434c77d79d048fba66f5748b0 (patch) | |
| tree | 0ba163f78104a2877f28c955682950f77847b8a8 /llvm | |
| parent | d8cadd6f174d3ba2cf74ea36ca4c825476920a2c (diff) | |
| download | bcm5719-llvm-98aa7fab7edf836434c77d79d048fba66f5748b0.tar.gz bcm5719-llvm-98aa7fab7edf836434c77d79d048fba66f5748b0.zip | |
[Sparc] Correct quad register list in the asm parser.
Add test cases to check parsing of v9 double registers and their aliased quad registers.
llvm-svn: 199974
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Sparc/sparc-fp.txt | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Sparc/sparc-fp-instructions.s | 6 |
3 files changed, 13 insertions, 1 deletions
diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index 07758894775..a4ea265a65d 100644 --- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -117,7 +117,7 @@ public: static unsigned QuadFPRegs[32] = { Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3, Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7, - Sparc::Q8, Sparc::Q7, Sparc::Q8, Sparc::Q9, + Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11, Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 }; diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-fp.txt b/llvm/test/MC/Disassembler/Sparc/sparc-fp.txt index 1cb3a5af16b..b8a5017383d 100644 --- a/llvm/test/MC/Disassembler/Sparc/sparc-fp.txt +++ b/llvm/test/MC/Disassembler/Sparc/sparc-fp.txt @@ -81,6 +81,12 @@ # CHECK: faddq %f0, %f4, %f8 0x91 0xa0 0x08 0x64 +# CHECK: faddd %f32, %f34, %f62 +0xbf 0xa0 0x48 0x43 + +# CHECK: faddq %f32, %f36, %f60 +0xbb 0xa0 0x48 0x65 + # CHECK: fsubs %f0, %f4, %f8 0x91 0xa0 0x08 0xa4 diff --git a/llvm/test/MC/Sparc/sparc-fp-instructions.s b/llvm/test/MC/Sparc/sparc-fp-instructions.s index 297be477040..7435a0a5e83 100644 --- a/llvm/test/MC/Sparc/sparc-fp-instructions.s +++ b/llvm/test/MC/Sparc/sparc-fp-instructions.s @@ -64,6 +64,12 @@ faddd %f0, %f4, %f8 faddq %f0, %f4, %f8 + ! make sure we can handle V9 double registers and their aliased quad registers. + ! CHECK: faddd %f32, %f34, %f62 ! encoding: [0xbf,0xa0,0x48,0x43] + ! CHECK: faddq %f32, %f36, %f60 ! encoding: [0xbb,0xa0,0x48,0x65] + faddd %f32, %f34, %f62 + faddq %f32, %f36, %f60 + ! CHECK: fsubs %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x08,0xa4] ! CHECK: fsubd %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x08,0xc4] ! CHECK: fsubq %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x08,0xe4] |
