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* ARM: Add GPR register class excluding LR for use with the ADR instruction.Tilmann Scheller2013-09-054-3/+99
| | | | | | | | | This improves code generation for jump tables by avoiding the emission of "mov pc, lr" which could fool the processor into believing this is a return from a function causing mispredicts. The code generation logic for jump tables uses ADR to materialize the address of the jump target. Patch by Daniel Stewart! llvm-svn: 190043
* [SystemZ] Add NC, OC and XCRichard Sandiford2013-09-0513-46/+999
| | | | | | | For now these are just used to handle scalar ANDs, ORs and XORs in which all operands are memory. llvm-svn: 190041
* Declare missing dependency on AliasAnalysis. Patch by Liu Xin!Nick Lewycky2013-09-051-0/+1
| | | | llvm-svn: 190035
* Fix typos in assert message.Nick Lewycky2013-09-051-1/+1
| | | | llvm-svn: 190034
* [Sparc] Correctly handle call to functions with ReturnsTwice attribute.Venkatraman Govindaraju2013-09-055-4/+116
| | | | | | | | | | | | In sparc, setjmp stores only the registers %fp, %sp, %i7 and %o7. longjmp restores the stack, and the callee-saved registers (all local/in registers: %i0-%i7, %l0-%l7) using the stored %fp and register windows. However, this does not guarantee that the longjmp will restore the registers, as they were when the setjmp was called. This is because these registers may be clobbered after returning from setjmp, but before calling longjmp. This patch prevents the registers %i0-%i5, %l0-l7 to live across the setjmp call using the register mask. llvm-svn: 190033
* msbuild: Add clang's compiler-rt libs to the LibraryPathReid Kleckner2013-09-051-0/+1
| | | | | | This allows linking libraries like the asan RTL. llvm-svn: 190028
* Fix comments to reflect reality.Bill Wendling2013-09-051-6/+2
| | | | llvm-svn: 190021
* Formatting.Eric Christopher2013-09-051-2/+2
| | | | llvm-svn: 190019
* Clean up some whitespace and comment formatting.Eric Christopher2013-09-051-21/+18
| | | | llvm-svn: 190015
* mi-sched: Force bottom up scheduling for generic targets.Andrew Trick2013-09-043-19/+34
| | | | | | | | | Fast register pressure tracking currently only takes effect during bottom up scheduling. Forcing this is a bit faster and simpler for targets that don't have many scheduling constraints and don't need top-down scheduling. llvm-svn: 190014
* Add names for mach-o permissions bits and use the symbol names in place of ↵Nick Kledzik2013-09-042-2/+13
| | | | | | magic numbers llvm-svn: 190013
* Move default dwarf version enum into the llvm dwarf constants ratherEric Christopher2013-09-041-3/+2
| | | | | | than the spec dwarf constants. llvm-svn: 190011
* fix typo in enum nameNick Kledzik2013-09-041-1/+1
| | | | llvm-svn: 190009
* Add missing header line.Bill Wendling2013-09-041-0/+1
| | | | llvm-svn: 190004
* Use ArrayRef instead of explicit container.Bill Wendling2013-09-041-2/+2
| | | | llvm-svn: 190003
* Remove hack ensuring that darwin didn't produce dwarf > 3 for modulesEric Christopher2013-09-047-35/+33
| | | | | | | | without a limiting factor. Update all testcases accordingly. llvm-svn: 190002
* Revert "Revert r189902 as the workaround shouldn't be necessary anymore."Eric Christopher2013-09-041-1/+5
| | | | | | Needs testcase updates. llvm-svn: 190000
* Revert r189902 as the workaround shouldn't be necessary anymore.Eric Christopher2013-09-041-5/+1
| | | | llvm-svn: 189999
* Expand and rewrite comment.Eric Christopher2013-09-041-3/+4
| | | | llvm-svn: 189998
* comment typoAndrew Trick2013-09-041-1/+1
| | | | llvm-svn: 189997
* Remove dead subtree limit code.Andrew Trick2013-09-041-9/+0
| | | | llvm-svn: 189995
* -view-misched-dags, better pruning.Andrew Trick2013-09-041-1/+1
| | | | llvm-svn: 189994
* mi-sched: DEBUG cleanup, call tracePick for unidirectional scheduling.Andrew Trick2013-09-041-0/+2
| | | | llvm-svn: 189993
* 80 columnsAndrew Trick2013-09-041-2/+2
| | | | llvm-svn: 189992
* mi-sched: Suppress register pressure tracking when the scheduling window is ↵Andrew Trick2013-09-042-18/+35
| | | | | | | | | | too small. If the instruction window is < NumRegs/2, pressure tracking is not likely to be effective. The scheduler has to process a very large number of tiny blocks. We want this to be fast. llvm-svn: 189991
* mi-sched: Load clustering is a bit to expensive to enable unconditionally.Andrew Trick2013-09-042-1/+3
| | | | llvm-svn: 189990
* mi-sched: Reuse an invalid HazardRecognizer to save compile time.Andrew Trick2013-09-041-6/+14
| | | | llvm-svn: 189989
* mi-sched: bypass heuristic checks when regpressure tracking is disabled.Andrew Trick2013-09-043-27/+35
| | | | llvm-svn: 189988
* Added -misched-regpressure option.Andrew Trick2013-09-044-23/+57
| | | | | | | | Register pressure tracking is half the complexity of the scheduler. It's useful to be able to turn it off for compile time and performance comparisons. llvm-svn: 189987
* Change swift/vldm test case to be less dependent on allocation orderArnold Schwaighofer2013-09-041-16/+16
| | | | | | | 'Force' values in registers using the calling convention. Now, we only depend on the calling convention and that the allocator performs copy coalescing. llvm-svn: 189985
* Rename some variables to match the style guide.Rafael Espindola2013-09-044-27/+27
| | | | | | I am about to patch this code, and this makes the diff far more readable. llvm-svn: 189982
* R600: Use shared op optimization when checking cycle compatibilityVincent Lejeune2013-09-042-0/+40
| | | | llvm-svn: 189981
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-09-0428-146/+299
| | | | llvm-svn: 189980
* R600: Use SchedModel enum for is{Trans,Vector}Only functionsVincent Lejeune2013-09-044-23/+19
| | | | llvm-svn: 189979
* R600: Remove fmul.v4f32.ll test which is redundant with fmul.llVincent Lejeune2013-09-041-15/+0
| | | | llvm-svn: 189978
* Unify and clean up.Eric Christopher2013-09-041-9/+4
| | | | llvm-svn: 189977
* Merge these 2 tests in a single file.Rafael Espindola2013-09-044-71/+50
| | | | llvm-svn: 189975
* ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane.Jim Grosbach2013-09-041-0/+7
| | | | | | | | | | | | | These instructions, such as vmul.f32, require the second source operand to be in D0-D15 rather than the full D0-D31. When optimizing, make sure to account for that by constraining the register class of a replacement virtual register to be compatible with the virtual register(s) it's replacing. I've been unsuccessful in creating a non-fragile regression test. This issue was detected by the LLVM nightly test suite running on an A15 (Bullet). PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093 llvm-svn: 189972
* Small simplification given that insert of an empty range is a nop.Rafael Espindola2013-09-041-2/+1
| | | | llvm-svn: 189971
* Remove 'param' label from comments. They aren't used properly here.Bill Wendling2013-09-041-15/+14
| | | | llvm-svn: 189970
* Refactor duplicated logic to a helper function.Rafael Espindola2013-09-041-36/+53
| | | | | | No functionality change. llvm-svn: 189969
* Remove dead code.Rafael Espindola2013-09-041-10/+0
| | | | llvm-svn: 189967
* MemoryBufer: add a test: check that a file with size that is a multiple of theDmitri Gribenko2013-09-041-0/+22
| | | | | | page size can be null terminated correctly by MemoryBuffer. llvm-svn: 189965
* Rename variables to match the style guide and clang-format.Rafael Espindola2013-09-042-71/+70
| | | | llvm-svn: 189962
* Swift: Only build vldm/vstm with q register aligned register listsArnold Schwaighofer2013-09-042-1/+32
| | | | | | | | Unaligned vldm/vstm need more uops and therefore are slower in general on swift. radar://14522102 llvm-svn: 189961
* Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes ↵Silviu Baranga2013-09-042-78/+125
| | | | | | on Cortex-A9. This also makes the existing code more compact. llvm-svn: 189958
* Revert "Add r159136 back now that pr13124 has been fixed."Rafael Espindola2013-09-043-31/+0
| | | | | | | | | | | | | | | | | | | This reverts commit r189886. I found a corner case where this optimization is not valid: Say we have a "linkonce_odr unnamed_addr" in two translation units: * In TU 1 this optimization kicks in and makes it hidden. * In TU 2 it gets const merged with a constant that is *not* unnamed_addr, resulting in a non unnamed_addr constant with default visibility. * The static linker rules for combining visibility them produce a hidden symbol, which is incorrect from the point of view of the non unnamed_addr constant. The one place we can do this is when we know that the symbol is not used from another TU in the same shared object, i.e., during LTO. I will move it there. llvm-svn: 189954
* Move generic isPrint and columnWidth implementations to a separate ↵Alexander Kornienko2013-09-049-220/+197
| | | | | | | | | | | | | | | | | | | | | header/source to allow using both generic and system-dependent versions on win32. Summary: This is needed so we can use generic columnWidthUTF8 in clang-format on win32 simultaneously with a separate system-dependent implementations of isPrint/columnWidth in TextDiagnostic.cpp to avoid attempts to print Unicode characters using narrow-character interfaces (which is not supported on Windows, and we'll have to figure out how to handle this). Reviewers: jordan_rose Reviewed By: jordan_rose CC: llvm-commits, klimek Differential Revision: http://llvm-reviews.chandlerc.com/D1559 llvm-svn: 189952
* Error on linking appending globals with different unnamed_addr.Rafael Espindola2013-09-043-1/+13
| | | | llvm-svn: 189950
* [Sparc] Fix an assertion failure while lowering fcmp on long double.Venkatraman Govindaraju2013-09-042-1/+21
| | | | | | | This assertion is triggered because an integer constant is created with wrong type. llvm-svn: 189948
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