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| author | Vincent Lejeune <vljn@ovi.com> | 2013-09-04 19:53:54 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-09-04 19:53:54 +0000 |
| commit | 744efa4dca205f44569089c8e9da6e10c77fafc4 (patch) | |
| tree | 8c8e7ff9bfda5514cf3d4f4bf97b44320a9f5284 /llvm | |
| parent | 7e2c83256bb55fcd634b055d72755f7724e89c54 (diff) | |
| download | bcm5719-llvm-744efa4dca205f44569089c8e9da6e10c77fafc4.tar.gz bcm5719-llvm-744efa4dca205f44569089c8e9da6e10c77fafc4.zip | |
R600: Use shared op optimization when checking cycle compatibility
llvm-svn: 189981
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/R600/R600InstrInfo.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/shared-op-cycle.ll | 38 |
2 files changed, 40 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/R600InstrInfo.cpp b/llvm/lib/Target/R600/R600InstrInfo.cpp index e3cb71b05c3..0e7cfb4354f 100644 --- a/llvm/lib/Target/R600/R600InstrInfo.cpp +++ b/llvm/lib/Target/R600/R600InstrInfo.cpp @@ -336,6 +336,8 @@ R600InstrInfo::ExtractSrcs(MachineInstr *MI, static std::vector<std::pair<int, unsigned> > Swizzle(std::vector<std::pair<int, unsigned> > Src, R600InstrInfo::BankSwizzle Swz) { + if (Src[0] == Src[1]) + Src[1].first = -1; switch (Swz) { case R600InstrInfo::ALU_VEC_012_SCL_210: break; diff --git a/llvm/test/CodeGen/R600/shared-op-cycle.ll b/llvm/test/CodeGen/R600/shared-op-cycle.ll new file mode 100644 index 00000000000..c49b5f4bd15 --- /dev/null +++ b/llvm/test/CodeGen/R600/shared-op-cycle.ll @@ -0,0 +1,38 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @main +; CHECK: MULADD_IEEE * +; CHECK-NOT: MULADD_IEEE * + +define void @main() { + %w0 = call float @llvm.R600.load.input(i32 3) + %w1 = call float @llvm.R600.load.input(i32 7) + %w2 = call float @llvm.R600.load.input(i32 11) + %sq0 = fmul float %w0, %w0 + %r0 = fadd float %sq0, 2.0 + %sq1 = fmul float %w1, %w1 + %r1 = fadd float %sq1, 2.0 + %sq2 = fmul float %w2, %w2 + %r2 = fadd float %sq2, 2.0 + %v0 = insertelement <4 x float> undef, float %r0, i32 0 + %v1 = insertelement <4 x float> %v0, float %r1, i32 1 + %v2 = insertelement <4 x float> %v1, float %r2, i32 2 + %res = call float @llvm.AMDGPU.dp4(<4 x float> %v2, <4 x float> %v2) + %vecres = insertelement <4 x float> undef, float %res, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %vecres, i32 0, i32 2) + ret void +} + +; Function Attrs: readnone +declare float @llvm.R600.load.input(i32) #1 + +; Function Attrs: readnone +declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 + + +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="1" } +attributes #1 = { readnone } +attributes #2 = { readonly } +attributes #3 = { nounwind readonly }
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