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* [Hexagon] Prettify code in HexagonDAGToDAGISel::SelectKrzysztof Parzyszek2017-02-241-47/+13
| | | | llvm-svn: 296187
* AMDGPU : Replace FMAD with FMA when denormals are enabled.Wei Ding2017-02-245-2/+39
| | | | | | Differential Revision: http://reviews.llvm.org/D29958 llvm-svn: 296186
* Revert "Correct register pressure calculation in presence of subregs"Stanislav Mekhanoshin2017-02-249-155/+30
| | | | | | | | This reverts commit r296009. It broke one out of tree target and also does not account for all partial lines added or removed when calculating PressureDiff. llvm-svn: 296182
* [utils] allow auto-generation of checks for thumb triplesSanjay Patel2017-02-241-0/+2
| | | | | | | If there's some reason not to do this, feel free to revert and/or fix, but for the cases I'm looking at, the script appears to do fine for these targets. llvm-svn: 296181
* Disallow redefinition of section symbols.Evgeniy Stepanov2017-02-246-143/+23
| | | | | | Differential Revision: https://reviews.llvm.org/D30235 llvm-svn: 296180
* Initialize MCContext::InlineSrcMgr in the constructor.Evgeniy Stepanov2017-02-241-2/+3
| | | | | | Found with ASan (and a local source change) on test/CodeGen/XCore/section-name.ll. llvm-svn: 296179
* [ARM] add tests for alternate forms of select-of-constants; NFCSanjay Patel2017-02-241-0/+33
| | | | llvm-svn: 296178
* [WebAssembly] Define an initial set of relocation types for Wasm.Dan Gohman2017-02-242-0/+17
| | | | | | This set will likely evolve, along with the Wasm linking ABI. llvm-svn: 296177
* GlobalISel: check for CImm rather than Imm on G_CONSTANTs.Tim Northover2017-02-242-6/+8
| | | | | | | All G_CONSTANTS created by the MachineIRBuilder have an operand of type CImm (i.e. a ConstantInt), so that's what the selector needs to look for. llvm-svn: 296176
* [ARM] auto-generate complete checks; NFCSanjay Patel2017-02-241-8/+34
| | | | | | | The affected test may change with a patch I'm looking at for DAGCombiner, so I want to make sure it's not a regression. llvm-svn: 296175
* [WebAssembly] Handle f16 in fast-isel.Dan Gohman2017-02-242-0/+3
| | | | llvm-svn: 296172
* Fix Indentation. NFCIXin Tong2017-02-241-2/+2
| | | | llvm-svn: 296169
* [Orc][RPC] Accept both const char* and char* arguments for string serialization.Lang Hames2017-02-242-4/+51
| | | | llvm-svn: 296168
* [CodeGenPrepare] Make -addr-sink-using-gep work with address spaces.Eli Friedman2017-02-242-7/+12
| | | | | | | | | | When we construct addressing modes, we use isNoopAddrSpaceCast to ignore addrspacecast instructions. Make sure we insert the correct addrspacecast when we reconstruct the addressing mode. Differential Revision: https://reviews.llvm.org/D30114 llvm-svn: 296167
* [InstCombine] Fix bug in pointer replacementYaxun Liu2017-02-242-1/+21
| | | | | | | | | | | This optimisation was crashing when there was a chain of more than one bitcast instruction to replace, as a result of the changes in D27283. Patch by James Price. Differential Revision: https://reviews.llvm.org/D30347 llvm-svn: 296163
* [Target/MIPS] Kill dead code, no functional change intended.Davide Italiano2017-02-241-11/+0
| | | | | | Hopefully placates gcc with -Werror. llvm-svn: 296153
* [CGP] Split some critical edges coming out of indirect branchesMichael Kuperstein2017-02-245-13/+435
| | | | | | | | | | | | | | | | | | | | | | Splitting critical edges when one of the source edges is an indirectbr is hard in general (because it requires changing the memory the indirectbr reads). But if a block only has a single indirectbr predecessor (which is the common case), we can simulate splitting that edge by splitting the destination block, and retargeting the *direct* branches. This is motivated by the use of computed gotos in python 2.7: PyEval_EvalFrame() ends up using an indirect branch with ~100 successors, and passing a constant to each of those. Since MachineSink can't break indirect critical edges on demand (and doing this in MIR doesn't look feasible), this causes us to emit about ~100 defs of registers containing constants, which we in the predecessor block, where only one of those constants is used in each successor. So, at each computed goto, we needlessly spill about a 100 constants to stack. The end result is that a clang-compiled python interpreter can be about ~2.5x slower on a simple python reduction loop than a gcc-compiled interpreter. Differential Revision: https://reviews.llvm.org/D29916 llvm-svn: 296149
* Revert: r296141 [APInt] Add APInt::extractBits() method to extract APInt ↵Simon Pilgrim2017-02-245-54/+8
| | | | | | | | | | | | | | | | | | subrange The current pattern for extract bits in range is typically: Mask.lshr(BitOffset).trunc(SubSizeInBits); Which can be particularly slow for large APInts (MaskSizeInBits > 64) as they require the allocation of memory for the temporary variable. This is another of the compile time issues identified in PR32037 (see also D30265). This patch adds the APInt::extractBits() helper method which avoids the temporary memory allocation. Differential Revision: https://reviews.llvm.org/D30336 llvm-svn: 296147
* [LV] Merge floating-point and integer induction widening codeMatthew Simpson2017-02-242-128/+148
| | | | | | | | | | | This patch merges the existing floating-point induction variable widening code into the integer induction variable widening code, creating a single set of functions for both kinds of inductions. The primary motivation for doing this is to enable vector phi node creation for floating-point induction variables. Differential Revision: https://reviews.llvm.org/D30211 llvm-svn: 296145
* [PowerPC] Use subfic instruction for subtract from immediateNemanja Ivanovic2017-02-242-0/+45
| | | | | | | | | | | Provide a 64-bit pattern to use SUBFIC for subtracting from a 16-bit immediate. The corresponding pattern already exists for 32-bit integers. Committing on behalf of Hiroshi Inoue. Differential Revision: https://reviews.llvm.org/D29387 llvm-svn: 296144
* [PowerPC] Use rldicr instruction for AND with an immediate if possibleNemanja Ivanovic2017-02-244-16/+35
| | | | | | | | | | | Emit clrrdi (extended mnemonic for rldicr) for AND-ing with masks that clear bits from the right hand size. Committing on behalf of Hiroshi Inoue. Differential Revision: https://reviews.llvm.org/D29388 llvm-svn: 296143
* [APInt] Add APInt::extractBits() method to extract APInt subrangeSimon Pilgrim2017-02-245-8/+54
| | | | | | | | | | | | | | | | The current pattern for extract bits in range is typically: Mask.lshr(BitOffset).trunc(SubSizeInBits); Which can be particularly slow for large APInts (MaskSizeInBits > 64) as they require the allocation of memory for the temporary variable. This is another of the compile time issues identified in PR32037 (see also D30265). This patch adds the APInt::extractBits() helper method which avoids the temporary memory allocation. Differential Revision: https://reviews.llvm.org/D30336 llvm-svn: 296141
* Fixed IntOperandMatcher::emitCxxPredicateExpr argumentsSimon Pilgrim2017-02-241-1/+1
| | | | | | Extra const in the StringRef argument meant that MSVC complained about it not correctly overriding from OperandPredicateMatcher::emitCxxPredicateExpr (which didn't have the const) llvm-svn: 296138
* [DAGCombiner] add missing folds for scalar select of {-1,0,1}Sanjay Patel2017-02-248-112/+72
| | | | | | | | | | | | | | | | | | | | | | | | The motivation for filling out these select-of-constants cases goes back to D24480, where we discussed removing an IR fold from add(zext) --> select. And that goes back to: https://reviews.llvm.org/rL75531 https://reviews.llvm.org/rL159230 The idea is that we should always canonicalize patterns like this to a select-of-constants in IR because that's the smallest IR and the best for value tracking. Note that we currently do the opposite in some cases (like the cases in *this* patch). Ie, the proposed folds in this patch already exist in InstCombine today: https://github.com/llvm-mirror/llvm/blob/master/lib/Transforms/InstCombine/InstCombineSelect.cpp#L1151 As this patch shows, most targets generate better machine code for simple ext/add/not ops rather than a select of constants. So the follow-up steps to make this less of a patchwork of special-case folds and missing IR canonicalization: 1. Have DAGCombiner convert any select of constants into ext/add/not ops. 2 Have InstCombine canonicalize in the other direction (create more selects). Differential Revision: https://reviews.llvm.org/D30180 llvm-svn: 296137
* Recommit "[mips] Fix atomic compare and swap at O0."Simon Dardis2017-02-249-154/+567
| | | | | | | | | | | | | | | | | | | | | | This time with the missing files. Similar to PR/25526, fast-regalloc introduces spills at the end of basic blocks. When this occurs in between an ll and sc, the store can cause the atomic sequence to fail. This patch fixes the issue by introducing more pseudos to represent atomic operations and moving their lowering to after the expansion of postRA pseudos. This resolves PR/32020. Thanks to James Cowgill for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D30257 llvm-svn: 296134
* Revert "[mips] Fix atomic compare and swap at O0."Simon Dardis2017-02-247-70/+154
| | | | | | This reverts r296132. I forgot to include the tests. llvm-svn: 296133
* [mips] Fix atomic compare and swap at O0.Simon Dardis2017-02-247-154/+70
| | | | | | | | | | | | | | | | | | | | Similar to PR/25526, fast-regalloc introduces spills at the end of basic blocks. When this occurs in between an ll and sc, the store can cause the atomic sequence to fail. This patch fixes the issue by introducing more pseudos to represent atomic operations and moving their lowering to after the expansion of postRA pseudos. This resolves PR/32020. Thanks to James Cowgill for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D30257 llvm-svn: 296132
* [globalisel] Decouple src pattern operands from dst pattern operands.Daniel Sanders2017-02-247-125/+538
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
* [X86][SSE] Target shuffle combine can try to combine up to 16 vectorsSimon Pilgrim2017-02-241-6/+6
| | | | | | Noticed while profiling PR32037, the target shuffle ops were being stored in SmallVector<*,8> types but the combiner could store as many as 16 ops at maximum depth (2 per depth). llvm-svn: 296130
* [InstCombine] don't try SimplifyDemandedInstructionBits from zext/sext ↵Sanjay Patel2017-02-241-10/+0
| | | | | | | | | | | | | | | | | | | | because it's slow and unnecessary This one seems more obvious than D30270 that it can't make improvements because an extension always needs all of the incoming bits. There's one specific transform in SimplifyDemandedInstructionBits of converting a sext to a zext when the sign-bit is known zero, but that is handled explicitly in visitSext() with ComputeSignBit(). Like D30270, there are no IR differences (other than instruction names) for the case in PR32037: https://bugs.llvm.org//show_bug.cgi?id=32037 ...and no regression test differences. Zext/sext are a smaller part of the profile, but this still appears to shave off another 0.5% or so from 'opt -O2'. Differential Revision: https://reviews.llvm.org/D30280 llvm-svn: 296129
* [x86] use DAG.getAllOnesConstant(); NFCISanjay Patel2017-02-241-18/+11
| | | | llvm-svn: 296128
* Fix missing call to base class constructor in r296121.Daniel Sanders2017-02-241-1/+3
| | | | | | | The 'Kind' member used in RTTI for InstructionPredicateMatcher was not initialized but went undetected since I always ended up with the correct value. llvm-svn: 296126
* [mips] Handle 64 bit immediate in and/or/xor pseudo instructions on mips64Simon Dardis2017-02-245-15/+555
| | | | | | | | | | | | | | | | | | | | Previously LLVM was assuming 32-bit signed immediates which results in and with a bitmask that has bit 31 set to incorrectly include bits 63-32 in the result. After applying this patch I can now compile all of the FreeBSD mips assembly code with clang. This issue also affects the nor, slt and sltu macros and I will fix those in a separate review. Patch By: Alexander Richardson Commit message reformatted by sdardis. Reviewers: atanasyan, theraven, sdardis Differential Revision: https://reviews.llvm.org/D30298 llvm-svn: 296125
* [ARM] GlobalISel: Select G_STOREDiana Picus2017-02-242-16/+70
| | | | | | Same as selecting G_LOAD. llvm-svn: 296122
* [globalisel] Sort RuleMatchers by priority.Daniel Sanders2017-02-241-2/+165
| | | | | | | | | | | | | | | | | | | | | | Summary: This makes more important rules have priority over less important rules. For example, '%a = G_ADD $b:s64, $c:s64' has priority over '%a = G_ADD $b:s32, $c:s32'. Previously these rules were emitted in the correct order by chance. NFC in this patch but it is required to make the next patch work correctly. Depends on D29710 Reviewers: t.p.northover, ab, qcolombet, aditya_nandakumar, rovka Reviewed By: ab, rovka Subscribers: javed.absar, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D29711 llvm-svn: 296121
* Minor test fixDiana Picus2017-02-241-2/+2
| | | | | | The test was using a size of 8 for loading/storing pointers. It should be 4. llvm-svn: 296120
* [ARM] GlobalISel: Add reg bank mappings for storesDiana Picus2017-02-242-0/+45
| | | | | | Same as the ones for loads. llvm-svn: 296115
* [mips][mc] Fix a crash when disassembling odd sized sectionsSimon Dardis2017-02-241-0/+1
| | | | | | Attempt to fix failing test. llvm-svn: 296112
* Fixup r296105 - only run tests on MipsDiana Picus2017-02-241-0/+3
| | | | llvm-svn: 296111
* Fix signed/unsigned comparison warningsSimon Pilgrim2017-02-241-4/+4
| | | | llvm-svn: 296109
* [ARM] GlobalISel: Legalize storesDiana Picus2017-02-242-3/+49
| | | | | | Allow the same types that we allow for loads. llvm-svn: 296108
* [mips][mc] Fix a crash when disassembling odd sized sectionsSimon Dardis2017-02-241-0/+16
| | | | | | Corresponding test. llvm-svn: 296106
* [mips][mc] Fix a crash when disassembling odd sized sectionsSimon Dardis2017-02-241-30/+21
| | | | | | | | | | | | | | Make the MIPS disassembler consistent with the other targets in returning a Size of zero when the input buffer cannot contain an instruction due to it's size. Previously it reported the minimum instruction size when it failed due to the buffer not being big enough for an instruction causing llvm-objdump to crash when disassembling all sections. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29984 llvm-svn: 296105
* Revert "[ARM] GlobalISel: Legalize stores"Diana Picus2017-02-242-42/+3
| | | | | | This reverts commit r296103 because the test broke on one of the bots. Sorry! llvm-svn: 296104
* [ARM] GlobalISel: Legalize storesDiana Picus2017-02-242-3/+42
| | | | | | Allow the same types that we allow for loads. llvm-svn: 296103
* [APInt] Add APInt::setBits() method to set all bits in rangeSimon Pilgrim2017-02-245-9/+136
| | | | | | | | | | | | | | | | | | The current pattern for setting bits in range is typically: Mask |= APInt::getBitsSet(MaskSizeInBits, LoPos, HiPos); Which can be particularly slow for large APInts (MaskSizeInBits > 64) as they require the allocation memory for the temporary variable. This is one of the key compile time issues identified in PR32037. This patch adds the APInt::setBits() helper method which avoids the temporary memory allocation completely, this first implementation uses setBit() internally instead but already significantly reduces the regression in PR32037 (~10% drop). Additional optimization may be possible. I investigated whether there is need for APInt::clearBits() and APInt::flipBits() equivalents but haven't seen these patterns to be particularly common, but reusing the code would be trivial. Differential Revision: https://reviews.llvm.org/D30265 llvm-svn: 296102
* Add missing initialization for MachineOptimizationRemarkEmitterJustin Bogner2017-02-241-0/+1
| | | | | | This was missed in r293110. llvm-svn: 296096
* [WebAssembly] Add a README.txt entry for mergeable sections.Dan Gohman2017-02-241-0/+5
| | | | llvm-svn: 296095
* [AVX-512] Separate the fadd/fsub/fmul/fdiv/fmax/fmin with rounding mode ISD ↵Craig Topper2017-02-245-26/+38
| | | | | | opcodes into separate packed and scalar opcodes. This is more consistent with the rest of the ISD opcodes. NFC llvm-svn: 296094
* [ExecutionDepsFix] Use range-based for loop. NFCCraig Topper2017-02-241-2/+1
| | | | llvm-svn: 296093
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