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author | Tim Northover <tnorthover@apple.com> | 2017-02-24 21:21:38 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2017-02-24 21:21:38 +0000 |
commit | ef29e7284b355e5ca8931e73bf6312d33a549c23 (patch) | |
tree | 97527a76f6ea7a01ec8d543b86b620f5068c61cb /llvm | |
parent | cd72f156d693aa61a93c1369daf51e43b9982c78 (diff) | |
download | bcm5719-llvm-ef29e7284b355e5ca8931e73bf6312d33a549c23.tar.gz bcm5719-llvm-ef29e7284b355e5ca8931e73bf6312d33a549c23.zip |
GlobalISel: check for CImm rather than Imm on G_CONSTANTs.
All G_CONSTANTS created by the MachineIRBuilder have an operand of type CImm
(i.e. a ConstantInt), so that's what the selector needs to look for.
llvm-svn: 296176
Diffstat (limited to 'llvm')
-rw-r--r-- | llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp | 7 | ||||
-rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect-xor.mir | 7 |
2 files changed, 8 insertions, 6 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp index a38ff00ed41..c1e4a8661a2 100644 --- a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp +++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp @@ -20,6 +20,7 @@ #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/IR/Constants.h" #include "llvm/IR/Function.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" @@ -187,8 +188,10 @@ bool InstructionSelector::isOperandImmEqual( MachineInstr *Def = MRI.getVRegDef(MO.getReg()); if (Def->getOpcode() != TargetOpcode::G_CONSTANT) return false; - assert(Def->getOperand(1).isImm() && "G_CONSTANT values must be constants"); - return Def->getOperand(1).getImm() == Value; + assert(Def->getOperand(1).isCImm() && + "G_CONSTANT values must be constants"); + const ConstantInt &Imm = *Def->getOperand(1).getCImm(); + return Imm.getBitWidth() <= 64 && Imm.getSExtValue() == Value; } return false; diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect-xor.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect-xor.mir index 2fd5588cadd..722dddb20a7 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect-xor.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect-xor.mir @@ -100,7 +100,7 @@ body: | liveins: %w0 %0(s32) = COPY %w0 - %1(s32) = G_CONSTANT -1 + %1(s32) = G_CONSTANT i64 -1 %2(s32) = G_XOR %0, %1 ... @@ -128,7 +128,7 @@ body: | liveins: %x0 %0(s64) = COPY %x0 - %1(s64) = G_CONSTANT -1 + %1(s64) = G_CONSTANT i64 -1 %2(s64) = G_XOR %0, %1 ... @@ -157,10 +157,9 @@ body: | bb.0: liveins: %w0, %w1 successors: %bb.1 - %1(s32) = G_CONSTANT -1 + %1(s32) = G_CONSTANT i64 -1 G_BR %bb.1 bb.1: %0(s32) = COPY %w0 %2(s32) = G_XOR %0, %1 ... - |