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* Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417Evan Cheng2011-12-082-0/+31
| | | | llvm-svn: 146196
* Remove reference to dead GEPSplitterPass. PR11506.Eli Friedman2011-12-081-6/+0
| | | | llvm-svn: 146195
* ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.Jim Grosbach2011-12-082-1/+5
| | | | llvm-svn: 146194
* Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter ↵Owen Anderson2011-12-086-16/+82
| | | | | | can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed. llvm-svn: 146193
* ARM VSHR implied destination operand form aliases.Jim Grosbach2011-12-084-0/+112
| | | | llvm-svn: 146192
* Add various missing AVX patterns which was causing crashes. Sadly, the generatedEvan Cheng2011-12-082-0/+95
| | | | | | | | code looks pretty bad compared to SSE. rdar://10538793 llvm-svn: 146191
* Tidy up a bit.Jim Grosbach2011-12-081-32/+37
| | | | llvm-svn: 146190
* Refactor. No intentional functionality change.Devang Patel2011-12-081-29/+41
| | | | llvm-svn: 146187
* Add rather verbose stats for fast-isel failures.Chad Rosier2011-12-081-0/+153
| | | | llvm-svn: 146186
* ARM asm parser, just issue a warning for a duplicate reg in a list.Jim Grosbach2011-12-081-1/+7
| | | | | | For better 'gas' compatibility. llvm-svn: 146185
* Filter "sink to" candidate blocks sooner. This avoids unnecessary ↵Devang Patel2011-12-081-11/+13
| | | | | | computation to determine whether the block dominates all uses or not. llvm-svn: 146184
* Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo inAkira Hatanaka2011-12-081-4/+11
| | | | | | | | MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the target is Mips64. llvm-svn: 146183
* ARM VSUB implied destination operand form aliases.Jim Grosbach2011-12-082-1/+48
| | | | llvm-svn: 146182
* Tidy up a bit.Jim Grosbach2011-12-081-10/+13
| | | | llvm-svn: 146181
* Don't explicitly marked libm rounding ops as legal on SSE4.1/AVX. There ↵Owen Anderson2011-12-081-11/+0
| | | | | | | | don't seem to be patterns for these, so I don't know why they were marked legal in the first place. Fixes failures caused by r146171. llvm-svn: 146180
* ARM VQADD implied destination operand form aliases.Jim Grosbach2011-12-082-16/+93
| | | | llvm-svn: 146179
* ARM a few more VMUL implied destination operand form aliases.Jim Grosbach2011-12-082-1/+40
| | | | llvm-svn: 146177
* Implement 64-bit support for thread local storage handling.Akira Hatanaka2011-12-085-55/+51
| | | | | | | | | | - Modify lowering of global TLS address nodes. - Modify isel of ThreadPointer. - Wrap target global TLS address nodes that are operands of loads with WrapperPIC. - Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be substituted with other existing nodes. llvm-svn: 146175
* Teach SelectionDAG to match more calls to libm functions onto existing ↵Owen Anderson2011-12-085-12/+81
| | | | | | SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise. llvm-svn: 146171
* ARM assembler support for register name aliases.Jim Grosbach2011-12-081-2/+16
| | | | | | rdar://10550084 llvm-svn: 146170
* Make MachineInstr instruction property queries more flexible. This change allEvan Cheng2011-12-082-63/+68
| | | | | | | | clients to decide whether to look inside bundled instructions and whether the query should return true if any / all bundled instructions have the queried property. llvm-svn: 146168
* Add test for r146163.Evan Cheng2011-12-081-0/+3
| | | | llvm-svn: 146167
* Many of the SSE patterns should not be selected when AVX is available. This ↵Evan Cheng2011-12-084-4/+11
| | | | | | | | | | | | | | | | | | led to the following code in X86Subtarget.cpp if (HasAVX) X86SSELevel = NoMMXSSE; This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected. However, this breaks instructions which do not have AVX variants. The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX(). Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change. However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case, the prefetch instructions. rdar://10538297 llvm-svn: 146163
* Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsicsDaniel Dunbar2011-12-082-324/+0
| | | | | | | sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).", it is failing tests. llvm-svn: 146157
* test/CodeGen/X86/vec_compare-2.ll: Add explicit -mtriple=i686-linux.NAKAMURA Takumi2011-12-081-1/+1
| | | | llvm-svn: 146152
* Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this ↵Jan Sjödin2011-12-082-14/+11
| | | | | | and fix the encoding. llvm-svn: 146151
* Fix a bug in the integer-promotion of bitcast operations on vector types.Nadav Rotem2011-12-084-2/+18
| | | | | | | We must not issue a bitcast operation for integer-promotion of vector types, because the location of the values in the vector may be different. llvm-svn: 146150
* Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵Stepan Dyatkovskiy2011-12-082-0/+324
| | | | | | for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). llvm-svn: 146143
* MTCTR needs to be glued to BCTR so that CTR is not marked dead in MTCTR ↵Hal Finkel2011-12-081-1/+1
| | | | | | (another find by -verify-machineinstrs) llvm-svn: 146137
* Reverting r145899 as it breaks clang self-hostingPete Cooper2011-12-081-0/+66
| | | | llvm-svn: 146136
* ARM NEON two-operand aliases for VSHL(immediate).Jim Grosbach2011-12-084-0/+55
| | | | llvm-svn: 146125
* Drop the HasInlineAsm flag.Jakob Stoklund Olesen2011-12-081-8/+2
| | | | | | | | | | It is not used any more. We are tracking inline assembly misalignments directly through the BBInfo.Unalign and KnownBits fields. A simple conservative size estimate is not good enough since it can cause alignment padding to be underestimated. llvm-svn: 146124
* ARM NEON two-operand aliases for VSHL(register).Jim Grosbach2011-12-082-0/+76
| | | | llvm-svn: 146123
* Simplify offset verification.Jakob Stoklund Olesen2011-12-081-9/+4
| | | | llvm-svn: 146121
* Fix copy/past-o.Jim Grosbach2011-12-081-2/+2
| | | | llvm-svn: 146120
* ARM NEON two-operand aliases for VMUL.Jim Grosbach2011-12-081-0/+5
| | | | llvm-svn: 146119
* Don't include alignment padding in BBInfo.Size.Jakob Stoklund Olesen2011-12-081-145/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | Compute alignment padding before and after basic blocks dynamically. Heed basic block alignment. This simplifies bookkeeping because we don't have to constantly add and remove padding from BBInfo.Size. It also makes it possible to track the extra known alignment bits we get after a tBR_JTr terminator and when entering an aligned basic block. This makes the ARMConstantIslandPass aware of aligned basic blocks. It is tricky to model block alignment correctly when dealing with inline assembly and tBR_JTr instructions that have variable size. If inline assembly turns out to be smaller than expected, that may cause following alignment padding to be larger than expected. This could cause constant pool entries to move out of range. To avoid that problem, we use the worst case alignment padding following inline assembly. This may cause slightly suboptimal constant island placement in aligned basic blocks following inline assembly. Normal functions should be unaffected. llvm-svn: 146118
* ARM VFP support 'fmrs/fmsr' aliases for 'vldr'Jim Grosbach2011-12-082-0/+3
| | | | llvm-svn: 146116
* ARM VFP support 'flds/fldd' aliases for 'vldr'Jim Grosbach2011-12-082-1/+7
| | | | llvm-svn: 146115
* ARM optional destination operand variants for VEXT instructions.Jim Grosbach2011-12-082-0/+32
| | | | llvm-svn: 146114
* Tidy up.Jim Grosbach2011-12-081-22/+29
| | | | llvm-svn: 146113
* Fix 80-column.Chad Rosier2011-12-082-11/+14
| | | | | | Simplify code. llvm-svn: 146112
* ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".Jim Grosbach2011-12-084-11/+62
| | | | llvm-svn: 146111
* Add Tsan annotations to the pass system.Nick Lewycky2011-12-081-1/+6
| | | | | | Perhaps once(&func) should be hoisted into lib/Support. llvm-svn: 146110
* Fix comments.Chad Rosier2011-12-082-1/+2
| | | | llvm-svn: 146109
* EngineBuilder: support for custom TargetOptions. Fixes thePeter Collingbourne2011-12-074-3/+19
| | | | | | ExceptionDemo example. llvm-svn: 146108
* Fix comments.Chad Rosier2011-12-072-3/+3
| | | | llvm-svn: 146107
* ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.Jim Grosbach2011-12-072-1/+5
| | | | | | For 'gas' compatibility. llvm-svn: 146106
* Modify class ReadHardware and add definition of 64-bit version of instructionAkira Hatanaka2011-12-072-3/+6
| | | | | | RDHWR. llvm-svn: 146101
* Add newline.Akira Hatanaka2011-12-071-1/+2
| | | | llvm-svn: 146100
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