| Commit message (Collapse) | Author | Age | Files | Lines | 
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Windows on ARM only supports thumb mode execution, so we have to
explicitly pick some non-Windows OS to test ARM mode codegen.
llvm-svn: 208638
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r208453 added support for having sret on the second parameter.  In that
change, the code for copying sret into a virtual register was hoisted
into the loop that lowers formal parameters.  This caused a "Wrong
topological sorting" assertion failure during scheduling when a
parameter is passed in memory.  This change undoes that by creating a
second loop that deals with sret.
I'm worried that this fix is incomplete.  I don't fully understand the
dependence issues.  However, with this change we produce the same DAGs
we used to produce, so if they are broken, they are just as broken as
they have always been.
llvm-svn: 208637
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time rather than as a post-processing step.
llvm-svn: 208636
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SECTDIFF relocations on 32-bit x86.
This fixes several of the MCJIT regression test failures that show up on 32-bit
builds.
<rdar://problem/16886294>
llvm-svn: 208635
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For some impending improvements to debug info, LLVM will start assuming
that when the CU specifies llvm::DIBuilder::LineTablesOnly, the IR for
functions described by that CU will not include variables, types, etc.
(might be worth having some test coverage for GMLT + non-GMLT CUs,
especially with non-GMLT functions inlined into GMLT CU functions)
llvm-svn: 208634
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instead of dyn_cast<>.
llvm-svn: 208628
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llvm-svn: 208627
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llvm-svn: 208622
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Tested by comparing make check VERBOSE=1 before and after to make sure
no tests are missed.  (VERBOSE=1 prints the list of tests.)
Only one test :( remains where .cpp is required:
tools/llvm-cov/range_based_for.cpp:// RUN: llvm-cov range_based_for.cpp | FileCheck %s --check-prefix=STDOUT
The topic was discussed in this thread:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140428/214905.html
llvm-svn: 208621
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The current patterns for REV16 misses mostn __builtin_bswap16() due to
legalization promoting the operands to from load/stores toi32s and then
truncing/extending them. This patch adds new patterns that catch the resultant
DAGs and codegens them to rev16 instructions. Tests included.
rdar://15353652
llvm-svn: 208620
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llvm-svn: 208618
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llvm-svn: 208617
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llvm-svn: 208615
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llvm-svn: 208614
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and reduce nesting/conditionals.
One test case had to be updated as it still had the extra indirection
for the variable list - removing the extra indirection got it back to
passing.
llvm-svn: 208608
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llvm-svn: 208607
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llvm-svn: 208606
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This is a slightly different approach to AArch64 (the base instruction
definitions aren't quite right for that to work), but achieves the
same thing and reduces C++ hackery in AsmParser.
llvm-svn: 208605
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llvm-svn: 208604
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llvm-svn: 208598
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llvm-svn: 208594
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llvm-svn: 208592
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folder.
llvm-svn: 208590
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llvm-svn: 208589
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folder.
llvm-svn: 208588
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llvm-svn: 208587
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llvm-svn: 208586
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test_3rf) into
correct folder.
llvm-svn: 208584
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Accidentally committed an unreviewed patch. Reverted it.
llvm-svn: 208583
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Summary:
Also use named constants for common opcode fields.
Depends on D3669
Reviewers: jkolek, vmedic, zoran.jovanovic
Differential Revision: http://reviews.llvm.org/D3670
llvm-svn: 208582
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llvm-svn: 208580
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Summary: Depends on D3668
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3669
llvm-svn: 208579
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There are some interesting decisions based on non-obvious rationale in
the ARM64-BE NEON implementation - decent documentation is definitely required.
llvm-svn: 208577
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Summary: The 'mul' line of the test is temporarily commented out because it currently matches the MIPS32 mul instead of the MIPS32r6 mul. This line will be uncommented when we disable the MIPS32 mul on MIPS32r6.
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3668
llvm-svn: 208576
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This lets us delete the MCAsmStreamer implementation. No functionality change.
llvm-svn: 208570
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No functionality change.
llvm-svn: 208569
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No functionality change.
llvm-svn: 208567
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(even though the switch is fully covered). No functional change.
llvm-svn: 208565
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If this code triggers, any immediate has already been validated so it can't
possibly trigger a diagnostic.
llvm-svn: 208564
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In terms of assembly, these have too much overlap to be neatly modelled as
disjoint classes: in many cases "lsl" is an acceptable alternative to either
"uxtw" or "uxtx".
llvm-svn: 208563
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Now that the asm streamer doesn't use it, the MCStreamer doesn't need to know
about it.
llvm-svn: 208562
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llvm-svn: 208561
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llvm-svn: 208559
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llvm-svn: 208558
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llvm-svn: 208557
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llvm-svn: 208555
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llvm-svn: 208554
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llvm-svn: 208553
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PR19721.
llvm-svn: 208552
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llvm-svn: 208551
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