X86: Make sure that we have SSE4.1 before we generate insertps nodes.

PR19721.

llvm-svn: 208552

2 files changed, 11 insertions, 1 deletions

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e134494a535..8d533bb08e0 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -5459,7 +5459,7 @@ static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
 
   SDValue V = FirstNonZero.getOperand(0);
   MVT VVT = V.getSimpleValueType();
-  if (VVT != MVT::v4f32 && VVT != MVT::v4i32)
+  if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
     return SDValue();
 
   unsigned FirstNonZeroDst =
diff --git a/llvm/test/CodeGen/X86/sse2.ll b/llvm/test/CodeGen/X86/sse2.ll
index 0a17eaca411..e8d3d6f19ed 100644
--- a/llvm/test/CodeGen/X86/sse2.ll
+++ b/llvm/test/CodeGen/X86/sse2.ll
@@ -229,3 +229,13 @@ define <2 x i64> @test_insert_64_zext(<2 x i64> %i) {
   %1 = shufflevector <2 x i64> %i, <2 x i64> <i64 0, i64 undef>, <2 x i32> <i32 0, i32 2>
   ret <2 x i64> %1
 }
+
+define <4 x i32> @PR19721(<4 x i32> %i) {
+  %bc = bitcast <4 x i32> %i to i128
+  %insert = and i128 %bc, -4294967296
+  %bc2 = bitcast i128 %insert to <4 x i32>
+  ret <4 x i32> %bc2
+
+; CHECK-LABEL: PR19721
+; CHECK: punpckldq
+}