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* Spill multiple registers at once.Jakob Stoklund Olesen2011-03-122-48/+210
| | | | | | | | | | | Live range splitting can create a number of small live ranges containing only a single real use. Spill these small live ranges along with the large range they are connected to with copies. This enables memory operand folding and maximizes the spill to fill distance. Work in progress with known bugs. llvm-svn: 127529
* Fixed the comparison operator for the enhancedSean Callanan2011-03-121-7/+2
| | | | | | disassembler's disassembler map. llvm-svn: 127527
* That's it, I am declaring this a failure of the C++03 STL.Jakob Stoklund Olesen2011-03-121-119/+15
| | | | | | | | | | | | | | There are too many compatibility problems with using mixed types in std::upper_bound, and I don't want to spend 110 lines of boilerplate setting up a call to a 10-line function. Binary search is not /that/ hard to implement correctly. I tried terminating the binary search with a linear search, but that actually made the algorithm slower against my expectation. Most live intervals have less than 4 segments. The early test against endIndex() does pay, and this version is 25% faster than plain std::upper_bound(). llvm-svn: 127522
* Saving files before committing is overrated.Eric Christopher2011-03-121-1/+1
| | | | | | Add a RUN line to this test. llvm-svn: 127520
* Sometimes isPredicable lies to us and tells us we don't need the operands.Eric Christopher2011-03-122-6/+85
| | | | | | | | | Go ahead and add them on when we might want to use them and let later passes remove them. Fixes rdar://9118569 llvm-svn: 127518
* Remove no-longer-correct special case for disasm of ARM BL instructions.Jim Grosbach2011-03-121-5/+0
| | | | llvm-svn: 127517
* Add FIXME.Jim Grosbach2011-03-121-0/+3
| | | | llvm-svn: 127516
* Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the sameJim Grosbach2011-03-122-27/+33
| | | | | | | | actual instruction as the non-Darwin defs, but have different call-clobber semantics and so need separate patterns. They don't need to duplicate the encoding information, however. llvm-svn: 127515
* Add a FIXME.Jim Grosbach2011-03-111-0/+2
| | | | llvm-svn: 127511
* Pseudo-ize the ARM 'B' instruction.Jim Grosbach2011-03-113-10/+14
| | | | llvm-svn: 127510
* Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach2011-03-112-9/+1
| | | | llvm-svn: 127509
* Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach2011-03-111-9/+0
| | | | llvm-svn: 127508
* Pseudo-ize VMOVDcc and VMOVScc.Jim Grosbach2011-03-113-9/+19
| | | | llvm-svn: 127506
* 80 columnsJim Grosbach2011-03-111-1/+2
| | | | llvm-svn: 127505
* Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-Jim Grosbach2011-03-1113-28/+32
| | | | | | effect that we get proper instruction printing using the "pop" mnemonic for it. llvm-svn: 127502
* Roll r127459 back in:Cameron Zwarich2011-03-1116-17/+31
| | | | | | | | | | | Optimize trivial branches in CodeGenPrepare, which often get created from the lowering of objectsize intrinsics. Unfortunately, a number of tests were relying on llc not optimizing trivial branches, so I had to add an option to allow them to continue to test what they originally tested. This fixes <rdar://problem/8785296> and <rdar://problem/9112893>. llvm-svn: 127498
* Fix the GCC test suite issue exposed by r127477, which was caused by stackCameron Zwarich2011-03-112-3/+22
| | | | | | | protector insertion not working correctly with unreachable code. Since that revision was rolled out, this test doesn't actual fail before this fix. llvm-svn: 127497
* Teach FastISel to support register-immediate-immediate instructions.Owen Anderson2011-03-112-9/+40
| | | | llvm-svn: 127496
* 80 columns.Jim Grosbach2011-03-111-2/+2
| | | | llvm-svn: 127495
* Trailing whitespace.Jim Grosbach2011-03-111-13/+13
| | | | llvm-svn: 127493
* Remove dead code. These ARM instruction definitions don't exist.Jim Grosbach2011-03-111-14/+0
| | | | llvm-svn: 127491
* ARM VDUPfd and VDUPfq can just be patterns. The instruction is the sameJim Grosbach2011-03-112-14/+2
| | | | | | as for VDUP32d and VDUP32q, respectively. llvm-svn: 127489
* Remove dead code. These ARM instruction definitions don't exist.Jim Grosbach2011-03-111-10/+0
| | | | llvm-svn: 127488
* ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32qJim Grosbach2011-03-113-12/+10
| | | | | | and VDUPLN32d, respectively. llvm-svn: 127486
* ARM VREV64df and VREV64qf can just be patterns. The instruction is the sameJim Grosbach2011-03-112-9/+2
| | | | | | as for VREV64d32 and VREV64q32, respectively. llvm-svn: 127485
* This FIXME has been fixed.Jim Grosbach2011-03-111-3/+0
| | | | llvm-svn: 127483
* Properly pseudo-ize ARM MVNCCi.Jim Grosbach2011-03-112-12/+15
| | | | llvm-svn: 127482
* Add missing 'return on failure'. Previously we'd crash after emittingJim Grosbach2011-03-111-0/+1
| | | | | | the diagnostic. llvm-svn: 127480
* Remove optimization emitting a reference insted of label difference, since ↵Jan Sjödin2011-03-113-21/+0
| | | | | | it can create more relocations. Removed isBaseAddressKnownZero method, because it is no longer used. llvm-svn: 127478
* Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often getDaniel Dunbar2011-03-1116-31/+17
| | | | | | created from the", it broke some GCC test suite tests. llvm-svn: 127477
* Force re-linking of LLVMgold.so when its exports file changes.Oscar Fuentes2011-03-111-0/+6
| | | | llvm-svn: 127473
* Fix processing of gold.exports.Oscar Fuentes2011-03-111-1/+1
| | | | llvm-svn: 127471
* While printing annotations, print line number and variable name if debug ↵Devang Patel2011-03-112-5/+50
| | | | | | info is present. llvm-svn: 127470
* Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4).Jim Grosbach2011-03-111-3/+3
| | | | llvm-svn: 127469
* Replace -dag-chain-limit flag with constant. It has survived a release cycle ↵Andrew Trick2011-03-111-3/+1
| | | | | | without being touched, so no longer needs to pollute the hidden-help text. llvm-svn: 127468
* Add LTO and gold plugin to the CMake build. Linux-only, support forOscar Fuentes2011-03-113-0/+58
| | | | | | | | other systems pending. PR9456. llvm-svn: 127466
* ComputeMaskedBits: sub falls through to add, and sub doesn't have the same ↵Benjamin Kramer2011-03-112-1/+12
| | | | | | | | overflow semantics as add. Should fix the selfhost failures that started with r127463. llvm-svn: 127465
* InstCombine: Fix a thinko where transform an icmp under the assumption that ↵Benjamin Kramer2011-03-112-3/+12
| | | | | | | | it's a zero comparison when it's not. Fixes PR9454. llvm-svn: 127464
* Teach ComputeMaskedBits about nsw on add. I don't think there's anything we canNick Lewycky2011-03-112-0/+24
| | | | | | | do with nuw here, but sub and mul should be given similar treatment. Fixes PR9343 #15! llvm-svn: 127463
* Fix use of CompEnd predicate to be standards conformingJohn Wiegley2011-03-111-9/+111
| | | | | | | | | | | | | The existing CompEnd predicate does not define a strict weak order as required by the C++03 standard; therefore, its use as a predicate to std::upper_bound is invalid. For a discussion of this issue, see http://www.open-std.org/jtc1/sc22/wg21/docs/lwg-defects.html#270 This patch replaces the asymmetrical comparison with an iterator adaptor that achieves the same effect while being strictly standard-conforming by ensuring an apples-to-apples comparison. llvm-svn: 127462
* Optimize trivial branches in CodeGenPrepare, which often get created from theCameron Zwarich2011-03-1116-17/+31
| | | | | | | | | | lowering of objectsize intrinsics. Unfortunately, a number of tests were relying on llc not optimizing trivial branches, so I had to add an option to allow them to continue to test what they originally tested. This fixes <rdar://problem/8785296> and <rdar://problem/9112893>. llvm-svn: 127459
* Teach TableGen to pre-calculate register enum values when creating theJim Grosbach2011-03-114-33/+36
| | | | | | | | | | | CodeGenRegister entries. Use this information to more intelligently build the literal register entires in the DAGISel matcher table. Specifically, use a single-byte OPC_EmitRegister entry for registers with a value of less than 256 and OPC_EmitRegister2 entry for registers with a larger value. rdar://9066491 llvm-svn: 127456
* silence a conditional assignment -Wuninitialized warning.Chris Lattner2011-03-111-1/+1
| | | | llvm-svn: 127453
* Make the register enum value part of the CodeGenRegister struct.Jim Grosbach2011-03-113-1/+8
| | | | llvm-svn: 127448
* Trailing whitespace.Jim Grosbach2011-03-112-33/+33
| | | | llvm-svn: 127447
* Trailing whitespace.Jim Grosbach2011-03-112-49/+49
| | | | llvm-svn: 127446
* Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos.Jim Grosbach2011-03-111-6/+6
| | | | llvm-svn: 127445
* Properly pseudo-ize ARM MOVCCi and MOVCCi16.Jim Grosbach2011-03-112-26/+30
| | | | llvm-svn: 127442
* Change the x86 32-bit scheduler to register pressure and fix up theEric Christopher2011-03-116-6/+11
| | | | | | | | corresponding testcases back to the previous versions. Fixes some performance regressions only seen on 32-bit. llvm-svn: 127441
* Avoid replacing the value of a directly stored load with the stored value if ↵Evan Cheng2011-03-112-2/+48
| | | | | | the load is indexed. rdar://9117613. llvm-svn: 127440
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