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* ARM disassembler was erroneously accepting an invalid RSC instruction.Johnny Chen2011-04-052-0/+15
| | | | | | | | Added checks for regs which should not be 15. rdar://problem/9237734 llvm-svn: 128945
* remove postdom frontiers, because it is dead. Forward dom frontiers areChris Lattner2011-04-059-904/+3
| | | | | | still used by RegionInfo :( llvm-svn: 128943
* docs/ReleaseNotes.html: Please use proper *Heading* elements instead of ↵NAKAMURA Takumi2011-04-051-61/+61
| | | | | | | | classified div. It would be better to browse without stylesheet. (eg. on ViewVC) llvm-svn: 128942
* ARM disassembler was erroneously accepting an invalid LSL instruction.Johnny Chen2011-04-052-0/+13
| | | | | | | | | For register-controlled shifts, we should check that the encoding constraint Inst{7} = 0 and Inst{4} = 1 is satisfied. rdar://problem/9237693 llvm-svn: 128941
* Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as ↵Owen Anderson2011-04-053-80/+76
| | | | | | doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions. llvm-svn: 128940
* remove graphprinter support for domfrontier.Chris Lattner2011-04-053-14/+5
| | | | llvm-svn: 128938
* These tests no longer require linear scan because reserved register ↵Jakob Stoklund Olesen2011-04-055-19/+14
| | | | | | coalescing is now universal. llvm-svn: 128936
* Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy.Jakob Stoklund Olesen2011-04-0511-1/+24
| | | | llvm-svn: 128935
* only 7 more weeks to go.Chris Lattner2011-04-051-5/+48
| | | | llvm-svn: 128933
* Refactor.Devang Patel2011-04-052-15/+21
| | | | llvm-svn: 128929
* Document llvm/ADT/IntEqClasses.h in ProgrammersManual.htmlJakob Stoklund Olesen2011-04-051-0/+21
| | | | llvm-svn: 128927
* Add an assertion instead of crashing when the scavenger goes past the endBob Wilson2011-04-051-1/+2
| | | | | | of a basic block. llvm-svn: 128925
* Fix typos. Adjust some whitespace for style. No functionality change.Nick Lewycky2011-04-052-14/+14
| | | | llvm-svn: 128924
* The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.Johnny Chen2011-04-052-7/+22
| | | | | | | | Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change. rdar://problem/9236873 llvm-svn: 128922
* Add support for detection of Intel SandyBridge.Roman Divacky2011-04-051-0/+2
| | | | llvm-svn: 128920
* Fix one more batch of X86 tests to be register allocation dependent.Jakob Stoklund Olesen2011-04-059-2797/+2811
| | | | llvm-svn: 128919
* When dead code elimination removes all but one use, try to fold the single ↵Jakob Stoklund Olesen2011-04-053-0/+56
| | | | | | | | def into the remaining use. Rematerialization can leave single-use loads behind that we might as well fold whenever possible. llvm-svn: 128918
* Do not emit empty name.Devang Patel2011-04-051-1/+2
| | | | llvm-svn: 128914
* ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.Johnny Chen2011-04-053-6/+15
| | | | llvm-svn: 128913
* Fix a typo.Andrew Trick2011-04-051-1/+1
| | | | llvm-svn: 128912
* Added *hidden* flags -print-options and -print-all-options soAndrew Trick2011-04-054-41/+436
| | | | | | | | | | | | | | | | | | | developers can see if their driver changed any cl::Option's. The current implementation isn't perfect but handles most kinds of options. This is nice to have when decomposing the stages of compilation and moving between different drivers. It's also a good sanity check when comparing results produced by different command line invocations that are expected to produce the comparable results. Note: This is not an attempt to prolong the life of cl::Option. On the contrary, it's a placeholder for a feature that must exist when cl::Option is replaced by a more appropriate framework. A new framework needs: a central option registry, dynamic name lookup, non-global containers of option values (e.g. per-module, per-function), *and* the ability to print options values and their defaults at any point during compilation. llvm-svn: 128910
* LDRD now prints out two dst registers.Johnny Chen2011-04-051-1/+1
| | | | llvm-svn: 128909
* Fix test-llvm failures.Johnny Chen2011-04-056-13/+13
| | | | llvm-svn: 128906
* whitespaceAndrew Trick2011-04-052-10/+10
| | | | llvm-svn: 128905
* An MCDisassembler has the option to not implementShantonu Sen2011-04-051-2/+4
| | | | | | | | | | getEDInfo(), in which case this code would dereference NULL. EDInst can already handle NULL info, so avoid the dereference and pass NULL through. Reviewed by Sean Callanan llvm-svn: 128904
* Make second source operand of LDRD pre/post explicit.Jim Grosbach2011-04-052-8/+28
| | | | | | Finish what r128736 started. llvm-svn: 128903
* more notes to self.Chris Lattner2011-04-051-6/+59
| | | | llvm-svn: 128902
* Constants with multiple encodings (ARM):Johnny Chen2011-04-053-8/+9
| | | | | | | | | | An alternative syntax is available for a modified immediate constant that permits the programmer to specify the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where: <byte> is the numeric value of abcdefgh, in the range 0-255 <rot> is twice the numeric value of rotation, an even number in the range 0-30. llvm-svn: 128897
* Check for invalid register encodings for UMAAL and friends where:Johnny Chen2011-04-052-2/+60
| | | | | | | | | if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; if dHi == dLo then UNPREDICTABLE; rdar://problem/9230202 llvm-svn: 128895
* Convert ADCS and SBCS instructions into pseudos that are expanded to the ↵Owen Anderson2011-04-052-41/+56
| | | | | | ADC/ABC with the appropriate S-bit input value. llvm-svn: 128892
* ARM doesn't support byval yet. XFAIL this test until it does.Stuart Hastings2011-04-051-0/+1
| | | | llvm-svn: 128891
* Rename LLVMConfig.cmake to LLVM-Config.cmake. The *Config.cmake namingOscar Fuentes2011-04-055-7/+7
| | | | | | scheme is used by the functionality related to find_package. llvm-svn: 128889
* Ensure all defs referring to a virtual register are marked dead by ↵Jakob Stoklund Olesen2011-04-052-8/+7
| | | | | | | | | | | | addRegisterDead(). There can be multiple defs for a single virtual register when they are defining sub-registers. The missing <dead> flag was stopping the inline spiller from eliminating dead code after rematerialization. llvm-svn: 128888
* Print visibility info for external variables.Rafael Espindola2011-04-052-12/+17
| | | | llvm-svn: 128887
* Use std::unique instead of a SmallPtrSet to ensure unique instructions in ↵Jakob Stoklund Olesen2011-04-053-54/+31
| | | | | | | | | | | UseSlots. This allows us to always keep the smaller slot for an instruction which is what we want when a register has early clobber defines. Drop the UsingInstrs set and the UsingBlocks map. They are no longer needed. llvm-svn: 128886
* InstCombine optimizes gep(bitcast(x)) even when the bitcasts casts away addressNadav Rotem2011-04-052-8/+27
| | | | | | | space info. We crash with an assert in this case. This change checks that the address space of the bitcasted pointer is the same as the gep ptr. llvm-svn: 128884
* docs/ReleaseNotes.html: Add a few notes to MCCOFF and x64. FIXME: fixme!NAKAMURA Takumi2011-04-051-8/+22
| | | | llvm-svn: 128882
* docs/GettingStarted.html: FIXME: dg, lit, and source tree layout.NAKAMURA Takumi2011-04-051-0/+10
| | | | llvm-svn: 128881
* add a bunch of notes to myself, this is not intended to be gramatic orChris Lattner2011-04-051-40/+82
| | | | | | make sense to anyone else. llvm-svn: 128879
* Stop precomputing last split points, query the SplitAnalysis cache on demand.Jakob Stoklund Olesen2011-04-053-21/+17
| | | | llvm-svn: 128875
* Cache the fairly expensive last split point computation and provide a fastJakob Stoklund Olesen2011-04-053-14/+58
| | | | | | | | | inlined path for the common case. Most basic blocks don't contain a call that may throw, so the last split point os simply the first terminator. llvm-svn: 128874
* Revamp the SjLj "dispatch setup" intrinsic.Bill Wendling2011-04-055-14/+11
| | | | | | | | | | | | It needed to be moved closer to the setjmp statement, because the code directly after the setjmp needs to know about values that are on the stack. Also, the 'bitcast' of the function context was causing a dead load. This wouldn't be too horrible, except that at -O0 it wasn't optimized out, and because it wasn't using the correct base pointer (if there is a VLA), it would try to access a value from a garbage address. <rdar://problem/9130540> llvm-svn: 128873
* Fix up testcase for previous commit.Eric Christopher2011-04-051-1/+1
| | | | llvm-svn: 128870
* Just use BL all the time. It's safer that way.Eric Christopher2011-04-051-9/+1
| | | | | | Fixes rdar://9184526 llvm-svn: 128869
* Revert 123704; it broke threaded LLVM.Stuart Hastings2011-04-051-9/+15
| | | | llvm-svn: 128868
* Fix register-dependent X86 tests.Jakob Stoklund Olesen2011-04-0530-76/+96
| | | | llvm-svn: 128867
* Fix SRS/SRSW encoding bits.Johnny Chen2011-04-053-0/+28
| | | | | | | | | rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with http://llvm.org/viewvc/llvm-project?view=rev&revision=128859. llvm-svn: 128864
* A8.6.105 MULJohnny Chen2011-04-041-1/+3
| | | | | | | | Inst{15-12} should be specified as 0b0000. rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL llvm-svn: 128862
* Add info on where to get 2.9 final svn sources.Bill Wendling2011-04-041-0/+1
| | | | llvm-svn: 128860
* RFE encoding should also specify the "should be" encoding bits.Johnny Chen2011-04-043-28/+49
| | | | | | | | | rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while doing regression testings. llvm-svn: 128859
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