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| author | Johnny Chen <johnny.chen@apple.com> | 2011-04-05 22:18:07 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-05 22:18:07 +0000 |
| commit | 9da60e016b51d02135a0ea63fc15b4c218c83400 (patch) | |
| tree | dd2f09b2b5590829dd0e0482172581cdbb967eec /llvm | |
| parent | 43d47cc397b15b1cd6b1efe39714d81e92230fbe (diff) | |
| download | bcm5719-llvm-9da60e016b51d02135a0ea63fc15b4c218c83400.tar.gz bcm5719-llvm-9da60e016b51d02135a0ea63fc15b4c218c83400.zip | |
ARM disassembler was erroneously accepting an invalid RSC instruction.
Added checks for regs which should not be 15.
rdar://problem/9237734
llvm-svn: 128945
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/invalid-RSC-arm.txt | 9 |
2 files changed, 15 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 786e001127f..db76c11b7b7 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -1072,6 +1072,12 @@ static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn, if (slice(insn, 7, 7)) return false; + // A8.6.3 ADC (register-shifted register) + // if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE; + if (decodeRd(insn) == 15 || decodeRn(insn) == 15 || + decodeRm(insn) == 15 || decodeRs(insn) == 15) + return false; + // Register-controlled shifts: [Rm, Rs, shift]. MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, decodeRs(insn)))); diff --git a/llvm/test/MC/Disassembler/ARM/invalid-RSC-arm.txt b/llvm/test/MC/Disassembler/ARM/invalid-RSC-arm.txt new file mode 100644 index 00000000000..e7992ae6342 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/invalid-RSC-arm.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE; +0x5f 0xf8 0xe4 0x30 |
