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* Fix a bug in llvm-objdump’s -private-headers for 32-bit Mach-O filesKevin Enderby2014-12-162-1/+337
| | | | | | printing the section header. And add some tests for this for 32-bit files. llvm-svn: 224302
* ARM/AArch64: Attach the FrameSetup MIFlag to CFI instructions.Adrian Prantl2014-12-165-13/+256
| | | | | | | | | | Debug info marks the first instruction without the FrameSetup flag as being the end of the function prologue. Any CFI instructions in the middle of the function prologue would cause debug info to end the prologue too early and worse, attach the line number of the CFI instruction, which incidentally is often 0. llvm-svn: 224294
* [Hexagon] Adding doubleword multiplies with and without accumulation.Colin LeMahieu2014-12-163-0/+148
| | | | llvm-svn: 224293
* Sink the isa into the assertMichael Ilseman2014-12-151-4/+2
| | | | llvm-svn: 224291
* [Hexagon] Adding halfword to doubleword multiplies.Colin LeMahieu2014-12-152-0/+83
| | | | llvm-svn: 224289
* [Hexagon] Adding logical-logical accumulation instructions and tests.Colin LeMahieu2014-12-152-19/+52
| | | | llvm-svn: 224288
* Teach ScalarEvolution to exploit min and max expressions when provingSanjoy Das2014-12-152-8/+546
| | | | | | | | | | | | | | | | isKnownPredicate. The motivation for this change is to optimize away checks in loops like this: limit = min(t, len) for (i = 0 to limit) if (i >= len || i < 0) throw_array_of_of_bounds(); a[i] = ... Differential Revision: http://reviews.llvm.org/D6635 llvm-svn: 224285
* Added missing tests for X86vzmovl folding. NFC.Simon Pilgrim2014-12-151-0/+37
| | | | llvm-svn: 224284
* x86: Emit LOCK prefix after DATA16JF Bastien2014-12-152-16/+18
| | | | | | | | | | | | | | Summary: x86 allows either ordering for the LOCK and DATA16 prefixes, but using GCC+GAS leads to different code generation than using LLVM. This change matches the order that GAS emits the x86 prefixes when a semicolon isn't used in inline assembly (see tc-i386.c comment before define LOCK_PREFIX), and helps simplify tooling that operates on the instruction's byte sequence (such as NaCl's validator). This change shouldn't have any performance impact. Test Plan: ninja check Reviewers: craig.topper, jvoung Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D6630 llvm-svn: 224283
* [Hexagon] Adding a number of additional multiply forms with tests.Colin LeMahieu2014-12-152-11/+146
| | | | llvm-svn: 224282
* Clean up warning about unused variableMichael Ilseman2014-12-151-2/+4
| | | | llvm-svn: 224281
* Revert "LiveRangeCalc: Rewrite subrange calculation"Matthias Braun2014-12-153-152/+242
| | | | | | | | Revert until I find out why non-subreg enabled targets break. This reverts commit 6097277eefb9c5fb35a7f493c783ee1fd1b9d6a7. llvm-svn: 224278
* Revert of r223763, in spirit.Michael Ilseman2014-12-151-2/+1
| | | | | | | | r223763 was made to work around a temporary issue where a user of the JIT was passing down a declaration (incorrectly). This shouldn't occur, so assert rather than silently continue. llvm-svn: 224277
* Clarify HowFarToZero computation when the step is a positive power of two. ↵Mark Heffernan2014-12-151-8/+13
| | | | | | Functionally this should be identical to the existing code except for the case where Step is maximally negative (eg, INT_MIN). We now punt in that one corner case to make reasoning about the code easier. llvm-svn: 224274
* [Hexagon] Adding misc multiply encodings and tests.Colin LeMahieu2014-12-152-0/+58
| | | | llvm-svn: 224273
* LiveRangeCalc: Rewrite subrange calculationMatthias Braun2014-12-153-242/+152
| | | | | | | | | This changes subrange calculation to calculate subranges sequentially instead of in parallel. The code is easier to understand that way and addresses the code review issues raised about LiveOutData being hard to understand/needing more comments by removing them :) llvm-svn: 224272
* [Hexagon] Adding doubleworld accumulating multiplies of halfwords.Colin LeMahieu2014-12-152-0/+106
| | | | llvm-svn: 224267
* [Hexagon] Adding accumulating half word multiplies.Colin LeMahieu2014-12-152-0/+153
| | | | llvm-svn: 224266
* [Hexagon] Adding multiply with rnd/sat/rndsatColin LeMahieu2014-12-152-0/+78
| | | | llvm-svn: 224265
* [X86] And also test INSERTPS shuffle mask pretty-printing.Ahmed Bougacha2014-12-151-0/+5
| | | | | | For r224260. llvm-svn: 224264
* LiveRangeCalc: use more range based for loops; NFCMatthias Braun2014-12-151-20/+18
| | | | llvm-svn: 224263
* [Hexagon] Adding encoding bits for halfword multiplies.Colin LeMahieu2014-12-152-0/+49
| | | | llvm-svn: 224261
* [X86] Also pretty-print shuffle mask for INSERTPS rm variants.Ahmed Bougacha2014-12-151-3/+7
| | | | llvm-svn: 224260
* IR: Make metadata typeless in assemblyDuncan P. N. Exon Smith2014-12-15703-11805/+11825
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that `Metadata` is typeless, reflect that in the assembly. These are the matching assembly changes for the metadata/value split in r223802. - Only use the `metadata` type when referencing metadata from a call intrinsic -- i.e., only when it's used as a `Value`. - Stop pretending that `ValueAsMetadata` is wrapped in an `MDNode` when referencing it from call intrinsics. So, assembly like this: define @foo(i32 %v) { call void @llvm.foo(metadata !{i32 %v}, metadata !0) call void @llvm.foo(metadata !{i32 7}, metadata !0) call void @llvm.foo(metadata !1, metadata !0) call void @llvm.foo(metadata !3, metadata !0) call void @llvm.foo(metadata !{metadata !3}, metadata !0) ret void, !bar !2 } !0 = metadata !{metadata !2} !1 = metadata !{i32* @global} !2 = metadata !{metadata !3} !3 = metadata !{} turns into this: define @foo(i32 %v) { call void @llvm.foo(metadata i32 %v, metadata !0) call void @llvm.foo(metadata i32 7, metadata !0) call void @llvm.foo(metadata i32* @global, metadata !0) call void @llvm.foo(metadata !3, metadata !0) call void @llvm.foo(metadata !{!3}, metadata !0) ret void, !bar !2 } !0 = !{!2} !1 = !{i32* @global} !2 = !{!3} !3 = !{} I wrote an upgrade script that handled almost all of the tests in llvm and many of the tests in cfe (even handling many `CHECK` lines). I've attached it (or will attach it in a moment if you're speedy) to PR21532 to help everyone update their out-of-tree testcases. This is part of PR21532. llvm-svn: 224257
* Silence more static analyzer warnings.Michael Ilseman2014-12-1513-11/+45
| | | | | | | | Add in definedness checks for shift operators, null checks when pointers are assumed by the code to be non-null, and explicit unreachables. llvm-svn: 224255
* Move mips1 tests to test/MC/Disassembler/Mips/mips1Reid Kleckner2014-12-153-0/+0
| | | | | | | This matches the pattern of the mips2 and 3 tests, as well as our normal conventions. llvm-svn: 224254
* Add disassembler tests for mips3 platform. There are no functional changes.Vladimir Medic2014-12-153-1/+420
| | | | llvm-svn: 224253
* Add disassembler tests for mips2 platform. There are no functional changes.Vladimir Medic2014-12-152-0/+318
| | | | llvm-svn: 224252
* This is the first in a series of patches that add missing disassembler tests ↵Vladimir Medic2014-12-153-0/+237
| | | | | | for mips platform. The patches are divided per version of mips CPU to keep the patches smaller and ease the review. There are no functional changes, code is changed only if new tests reveal a bug.This patch adds disassembler tests for mips1 CPU. llvm-svn: 224251
* Changing a cast from unsigned to uint64_t, should be NFC in practice.Aaron Ballman2014-12-151-1/+1
| | | | llvm-svn: 224249
* Added a test related to 224247 revisionElena Demikhovsky2014-12-151-0/+43
| | | | llvm-svn: 224248
* Sink store based on alias analysisElena Demikhovsky2014-12-154-63/+63
| | | | | | | | | | | | - by Ella Bolshinsky The alias analysis is used define whether the given instruction is a barrier for store sinking. For 2 identical stores, following instructions are checked in the both basic blocks, to determine whether they are sinking barriers. http://reviews.llvm.org/D6420 llvm-svn: 224247
* [X86] Break false dependencies before partial register updates when the ↵Michael Kuperstein2014-12-153-43/+120
| | | | | | | | | | source operand is in memory Adds the various "rm" instruction variants into the list of instructions that have a partial register update. Also adds all variants of SQRTSD that were missing in the original list. Differential Revision: http://reviews.llvm.org/D6620 llvm-svn: 224246
* Typo Correction in Test Case. NFC.Suyog Sarda2014-12-151-1/+1
| | | | llvm-svn: 224244
* AVX-512: Added EXPAND instructions and intrinsics.Elena Demikhovsky2014-12-156-15/+343
| | | | llvm-svn: 224241
* Fix line mapping information in LLVM JIT profiling with VtuneAlexey Bataev2014-12-152-1/+13
| | | | | | | | The line mapping information for dynamic code is reported incorrectly. It causes VTune to map LLVM generated code to source lines incorrectly. This patch fix this issue. Patch by Denis Pravdin. Differential Revision: http://reviews.llvm.org/D6603 llvm-svn: 224229
* ThreadLocal: Move Unix-specific code out of Support/ThreadLocal.cppDavid Majnemer2014-12-152-45/+43
| | | | | | Just a cleanup, no functionality change is intended. llvm-svn: 224227
* StringPool: Cleanup typos in unittest commentsDavid Majnemer2014-12-151-2/+2
| | | | | | No functional change intended. llvm-svn: 224226
* ThreadLocal: Return a mutable pointer if templated with a non-const typeDavid Majnemer2014-12-155-7/+26
| | | | | | | It makes more sense for ThreadLocal<const T>::get to return a const T* and ThreadLocal<T>::get to return a T*. llvm-svn: 224225
* Use unique_ptr to remove explicit delete.Craig Topper2014-12-153-9/+9
| | | | llvm-svn: 224224
* Loop Vectorizer minor changes in the code - Elena Demikhovsky2014-12-144-14/+14
| | | | | | | | some comments, function names, identation. Reviewed here: http://reviews.llvm.org/D6527 llvm-svn: 224218
* APInt: udivrem should use machine instructions for single-word APIntsDavid Majnemer2014-12-141-0/+12
| | | | | | | | This mirrors the behavior of APInt::udiv and APInt::urem. Some architectures, like X86, have a single instruction which can compute both division and remainder. llvm-svn: 224217
* ScalarEvolution: Remove SCEVUDivision, it's unusedDavid Majnemer2014-12-141-93/+26
| | | | | | This is just a code simplification, no functionality change is intended. llvm-svn: 224216
* [PowerPC] Handle cmp op promotion for SELECT[_CC] nodes in ↵Hal Finkel2014-12-142-18/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PPCTL::DAGCombineExtBoolTrunc PPCTargetLowering::DAGCombineExtBoolTrunc contains logic to remove unwanted truncations and extensions when dealing with nodes of the form: zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...) There was a FIXME in the implementation (now removed) regarding the fact that the function would abort the transformations if any of the non-output operands of a SELECT or SELECT_CC node would need to be promoted (because they were also output operands, for example). As a result, we continued to generate unnecessary zero-extends for code such as this: unsigned foo(unsigned a, unsigned b) { return (a <= b) ? a : b; } which would produce: cmplw 0, 3, 4 isel 3, 4, 3, 1 rldicl 3, 3, 0, 32 blr and now we produce: cmplw 0, 3, 4 isel 3, 4, 3, 1 blr which is better in the obvious way. llvm-svn: 224213
* Reapply "[ARM] Combine base-updating/post-incrementing vector load/stores."Ahmed Bougacha2014-12-136-27/+485
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | r223862 tried to also combine base-updating load/stores. r224198 reverted it, as "it created a regression on the test-suite on test MultiSource/Benchmarks/Ptrdist/anagram by scrambling the order in which the words are shown." Reapply, with a fix to ignore non-normal load/stores. Truncstores are handled elsewhere (you can actually write a pattern for those, whereas for postinc loads you can't, since they return two values), but it should be possible to also combine extloads base updates, by checking that the memory (rather than result) type is of the same size as the addend. Original commit message: We used to only combine intrinsics, and turn them into VLD1_UPD/VST1_UPD when the base pointer is incremented after the load/store. We can do the same thing for generic load/stores. Note that we can only combine the first load/store+adds pair in a sequence (as might be generated for a v16f32 load for instance), because other combines turn the base pointer addition chain (each computing the address of the next load, from the address of the last load) into independent additions (common base pointer + this load's offset). Differential Revision: http://reviews.llvm.org/D6585 llvm-svn: 224203
* Revert "[ARM] Combine base-updating/post-incrementing vector load/stores."Renato Golin2014-12-136-421/+27
| | | | | | | | | This reverts commit r223862, as it created a regression on the test-suite on test MultiSource/Benchmarks/Ptrdist/anagram by scrambling the order in which the words are shown. We'll investigate the issue and re-apply when safe. llvm-svn: 224198
* Fix Doxygen command misspellings.Benjamin Kramer2014-12-132-3/+3
| | | | | | Found by -Wdocumentation. llvm-svn: 224197
* Silencing a -Wsign-compare warning; NFC.Aaron Ballman2014-12-131-1/+2
| | | | llvm-svn: 224195
* Silencing a *lot* of -Wsign-compare warnings; NFC.Aaron Ballman2014-12-131-1/+2
| | | | llvm-svn: 224194
* Use range-based for loops.Craig Topper2014-12-131-52/+35
| | | | llvm-svn: 224187
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