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* GCC has supported C++11 ref-qualifiers since 4.8.1Reid Kleckner2014-10-212-25/+29
| | | | | | | | | | | | This requires incorporating __GNUC_PATCHLEVEL__ into our prerequisite check, and renaming our __GNUC_PREREQ to LLVM_GNUC_PREREQ, since it is now functionally different. Patch by Chilledheart! Differential Revision: http://reviews.llvm.org/D5879 llvm-svn: 220332
* R600: Use default GlobalDirectiveMatt Arsenault2014-10-212-1/+14
| | | | | | | The overridden one wasn't inserting a space, so you would end up with .globalfoo llvm-svn: 220329
* Use a StringRef. No functionality change.Rafael Espindola2014-10-211-5/+4
| | | | llvm-svn: 220327
* Teach combineMetadata how to merge 'nonnull' metadata.Philip Reames2014-10-211-0/+4
| | | | | | combineMetadata is used when merging two instructions into one. This change teaches it how to merge 'nonnull' - i.e. only preserve it on the new instruction if it's set on both sources. This isn't actually used yet since I haven't adjusted any of the call sites to pass in nonnull as a 'known metadata'. llvm-svn: 220325
* Preserve 'nonnull' when changing type of the load.Philip Reames2014-10-211-0/+1
| | | | | | | | When changing the type of a load in Chandler's recent InstCombine changes, we can preserve the new 'nonnull' metadata. I considered adding an assert since 'nonnull' is only valid on pointer types, but casting a pointer to a non-pointer would involve more than a bitcast anyways. If someone extends this transform to handle more than bitcasts, the verifier will report the malformed IR, so a separate assertion isn't needed. Also, the fpmath flags would have the same problem. llvm-svn: 220324
* Extend the verifier to check usage of 'nonnull' metadata.Philip Reames2014-10-211-0/+8
| | | | | | The recently added !nonnull metadata is only valid on loads of pointer type. llvm-svn: 220323
* [PBQP] Teach PassConfig to tell if the default register allocator is used.Arnaud A. de Grandmaison2014-10-215-19/+14
| | | | | | | | This enables targets to adapt their pass pipeline to the register allocator in use. For example, with the AArch64 backend, using PBQP with the cortex-a57, the FPLoadBalancing pass is no longer necessary. llvm-svn: 220321
* Move code a bit to avoid a few declarations. NFC.Rafael Espindola2014-10-211-45/+40
| | | | llvm-svn: 220317
* [PBQP] Add a testcase for r220302: Fix coalescing benefitsArnaud A. de Grandmaison2014-10-211-0/+14
| | | | llvm-svn: 220316
* InstCombine: Simplify FoldICmpCstShrCstDavid Majnemer2014-10-214-378/+348
| | | | | | | | | This function was complicated by the fact that it tried to perform canonicalizations that were already preformed by InstSimplify. Remove this extra code and move the tests over to InstSimplify. Add asserts to make sure our preconditions hold before we make any assumptions. llvm-svn: 220314
* Drop support for an old version of ld64 (from darwin 9).Rafael Espindola2014-10-217-57/+3
| | | | llvm-svn: 220310
* remove function names from comments; NFCSanjay Patel2014-10-211-2/+2
| | | | llvm-svn: 220309
* Convert two tests to use llvm-readobj.Rafael Espindola2014-10-212-32/+41
| | | | llvm-svn: 220308
* R600/SI: Add pattern for bswapMatt Arsenault2014-10-214-1/+84
| | | | llvm-svn: 220304
* [PBQP] Check for out of bound access in DEBUG buildsArnaud A. de Grandmaison2014-10-211-2/+8
| | | | | | | | It is just too easy to use a virtual register intead of a NodeId without a compiler warning. This does not fix the fundamental problem, i.e. both have the same underlying types, but increases the likelyhood to detect it. llvm-svn: 220303
* [PBQP] Fix coalescing benefitsArnaud A. de Grandmaison2014-10-211-2/+2
| | | | | | As coalescing registers is a benefit, the cost should be improved (i.e. made smaller) when coalescing is possible. llvm-svn: 220302
* X86AsmInstrumentation.cpp: Dissolve initializer-ranged-for. MSC17 disliked it.NAKAMURA Takumi2014-10-211-3/+3
| | | | llvm-svn: 220301
* Silence a -Wcast-qual warning; NFC.Aaron Ballman2014-10-211-1/+1
| | | | llvm-svn: 220300
* Test commitColin LeMahieu2014-10-211-1/+1
| | | | | | Fixing brief comment. llvm-svn: 220299
* Comment cleanup. NFC.Rafael Espindola2014-10-211-16/+14
| | | | | | | Don't duplicate names in comments and remove useless ones. Hopefully anyone reading this knows what main is. llvm-svn: 220298
* Add support for addmod to mri scripts.Rafael Espindola2014-10-212-1/+23
| | | | llvm-svn: 220294
* [PowerPC] Avoid VSX FMA mutate when killed product reg = addend regBill Schmidt2014-10-213-2/+29
| | | | | | | | | | | | | | | | | | | | | With VSX enabled, test/CodeGen/PowerPC/recipest.ll exposes a bug in the FMA mutation pass. If we have a situation where a killed product register is the same register as the FMA target, such as: %vreg5<def,tied1> = XSNMSUBADP %vreg5<tied0>, %vreg11, %vreg5, %RM<imp-use>; VSFRC:%vreg5 F8RC:%vreg11 then the substitution makes no sense. We end up getting a crash when we try to extend the interval associated with the killed product register, as there is already a live range for %vreg5 there. This patch just disables the mutation under those circumstances. Since recipest.ll generates different code with VMX enabled, I've modified that test to use -mattr=-vsx. I've borrowed the code from that test that exposed the bug and placed it in fma-mutate.ll, where it tests several mutation opportunities including the "bad" one. llvm-svn: 220290
* [ARM] NEON 32-bit scalar moves are also available in VFPv2Oliver Stannard2014-10-212-2/+35
| | | | | | | | | | | The 32-bit variants of the NEON scalar<->GPR move instructions are also available in VFPv2. The 8- and 16-bit variants do require NEON. Note that the checks in the test file are all -DAG because they are checking a mixture of stdout and stderr, and the ordering is not guaranteed. llvm-svn: 220288
* [asan-asm-instrumentation] Fixed memory accesses with rbp as a base or an ↵Yuri Gorshenin2014-10-212-83/+135
| | | | | | | | | | | | | | index register. Summary: Fixed memory accesses with rbp as a base or an index register. Reviewers: eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5819 llvm-svn: 220283
* [Thumb2] LDRS?[BH] cannot load to the PCOliver Stannard2014-10-212-4/+55
| | | | | | | The Thumb2 LDRS?[BH] instructions are not valid when the destination register is the PC (these encodings are used for preload hints). llvm-svn: 220278
* Teach the load analysis to allow finding available values which requireChandler Carruth2014-10-217-18/+136
| | | | | | | | | | | | | | | | | | | | inttoptr or ptrtoint cast provided there is datalayout available. Eventually, the datalayout can just be required but in practice it will always be there today. To go with the ability to expose available values requiring a ptrtoint or inttoptr cast, helpers are added to perform one of these three casts. These smarts are necessary to finish canonicalizing loads and stores to the operational type requirements without regressing fundamental combines. I've added some test cases. These should actually improve as the load combining and store combining improves, but they may fundamentally be highlighting some missing combines for select in addition to exercising the specific added logic to load analysis. llvm-svn: 220277
* [mips][microMIPS] Implement ADDU16 and SUBU16 instructionsZoran Jovanovic2014-10-214-0/+35
| | | | | | Differential Revision: http://reviews.llvm.org/D5118 llvm-svn: 220276
* [mips][microMIPS] Implement AND16, NOT16, OR16 and XOR16 instructionsZoran Jovanovic2014-10-214-0/+50
| | | | | | Differential Revision: http://reviews.llvm.org/D5117 llvm-svn: 220275
* [mips][microMIPS] Implement microMIPS 16-bit instructions registersZoran Jovanovic2014-10-213-0/+46
| | | | | | Differential Revision: http://reviews.llvm.org/D5116 llvm-svn: 220273
* Fix a bit of confusion about .set and produce more readable assembly.Rafael Espindola2014-10-2115-91/+63
| | | | | | | | | | | | | | | Every target we support has support for assembly that looks like a = b - c .long a What is special about MachO is that the above combination suppresses the production of a relocation. With this change we avoid producing the intermediary labels when they don't add any value. llvm-svn: 220256
* Do not attribute static allocas to the call site's DebugLoc.Paul Robinson2014-10-212-0/+149
| | | | | | | | | | | | | When functions are inlined, instructions without debug information are attributed to the call site's DebugLoc. After inlining, inlined static allocas are moved to the caller's entry block, adjacent to the caller's original static alloca instructions. By retaining the call site's DebugLoc, these instructions could cause instructions that were subsequently inserted at the entry block to pick up the same DebugLoc. Patch by Wolfgang Pieb! llvm-svn: 220255
* Make this test a bit more strict.Rafael Espindola2014-10-211-6/+11
| | | | llvm-svn: 220253
* Teach lit to filter the host LDFLAGS down from the build system and intoChandler Carruth2014-10-215-1/+5
| | | | | | | | | | the CGO build environment. This lets things like -rpath propagate down to the C++ code that is built along side the Go bindings when testing them. Patch by Peter Collingbourne, and verified that it works by me. llvm-svn: 220252
* PR21202: Memory leak in Windows RWMutexImpl when using SRWLOCKDavid Blaikie2014-10-211-5/+3
| | | | llvm-svn: 220251
* Make AsmPrinter::EmitLabelOffsetDifference a static helper and simplify.Rafael Espindola2014-10-213-39/+27
| | | | | | It had exactly one caller in a position where we know hasSetDirective is true. llvm-svn: 220250
* [MCJIT] Temporarily revert r220245 - it broke several bots.Lang Hames2014-10-2110-62/+7
| | | | | | (See e.g. http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/17653) llvm-svn: 220249
* Introduce enum values for previously defined metadata types. (NFC)Philip Reames2014-10-218-15/+33
| | | | | | | | | | | Our metadata scheme lazily assigns IDs to string metadata, but we have a mechanism to preassign them as well. Using a preassigned ID is helpful since we get compile time type checking, and avoid some (minimal) string construction and comparison. This change adds enum value for three existing metadata types: + MD_nontemporal = 9, // "nontemporal" + MD_mem_parallel_loop_access = 10, // "llvm.mem.parallel_loop_access" + MD_nonnull = 11 // "nonnull" I went through an updated various uses as well. I made no attempt to get all uses; I focused on the ones which were easily grepable and easily to translate. For example, there were several items in LoopInfo.cpp I chose not to update. llvm-svn: 220248
* Extend the verifier to validate range metadata on calls and invokes.Philip Reames2014-10-202-52/+68
| | | | | | Range metadata applies to loads, call, and invokes. We were validating that metadata applied to loads was correct according to the LangRef, but we were not validating metadata applied to calls or invokes. This change extracts the checking functionality to a common location, reuses it for all valid locations, and adds a simple test to ensure a misused range on a call gets reported. llvm-svn: 220246
* [MCJIT] Make MCJIT honor symbol visibility settings when populating the globalLang Hames2014-10-2010-7/+62
| | | | | | | | symbol table. Patch by Anthony Pesch. Thanks Anthony! llvm-svn: 220245
* [X86] Fix a bug in the lowering of the mask of VSELECT.Quentin Colombet2014-10-202-1/+33
| | | | | | | | | | | | | | | | X86 code to lower VSELECT messed a bit with the bits set in the mask of VSELECT when it knows it can be lowered into BLEND. Indeed, only the high bits need to be set for those and it optimizes those accordingly. However, when the mask is a compile time constant, the lowering will be handled by the generic optimizer and those modifications will generate bad code in the generic optimizer. This patch fixes that by preventing the optimization if the VSELECT will be handled by the generic optimizer. <rdar://problem/18675020> llvm-svn: 220242
* Introduce a 'nonnull' metadata on Load instructions.Philip Reames2014-10-203-1/+36
| | | | | | | | | The newly introduced 'nonnull' metadata is analogous to existing 'nonnull' attributes, but applies to load instructions rather than call arguments or returns. Long term, it would be nice to combine these into a single construct. The value of the load is allowed to vary between successive loads, but null is not a valid value to be loaded by any load marked nonnull. Reviewed by: Hal Finkel Differential Revision: http://reviews.llvm.org/D5220 llvm-svn: 220240
* [X86] Memory folding for commutative instructions (updated)Simon Pilgrim2014-10-205-59/+202
| | | | | | | | | | | | This patch improves support for commutative instructions in the x86 memory folding implementation by attempting to fold a commuted version of the instruction if the original folding fails - if that folding fails as well the instruction is 're-commuted' back to its original order before returning. Updated version of r219584 (reverted in r219595) - the commutation attempt now explicitly ensures that neither of the commuted source operands are tied to the destination operand / register, which was the source of all the regressions that occurred with the original patch attempt. Added additional regression test case provided by Joerg Sonnenberger. Differential Revision: http://reviews.llvm.org/D5818 llvm-svn: 220239
* Explain why we don't always use --gc-sections.Rafael Espindola2014-10-201-0/+4
| | | | llvm-svn: 220237
* ARM: rework Thumb1 frame index rewritingTim Northover2014-10-206-114/+102
| | | | | | | | | | | | | | | | | | | | | | | The previous code had a few problems, motivating the choices here. 1. It could create instructions clobbering CPSR, but the incoming MachineInstr didn't reflect this. A potential source of corruption. This is why the patch has a new PseudoInst for before lowering. 2. Similarly, there was some code to handle the incoming instruction not being ARMCC::AL, but this would have caused massive problems if it was actually invoked when a complex offset needing more than one instruction was requested. 3. It wasn't designed to handle unaligned pointers (or offsets). These should probably be minimised anyway, but the code needs to deal with them properly regardless. 4. It had some rather dubious ad-hoc code to avoid calling emitThumbRegPlusImmediate, a function which should be designed to do precisely this job. We seem to cover the common cases correctly now, and hopefully can enhance emitThumbRegPlusImmediate to handle any extra optimisations we need to add in future. llvm-svn: 220236
* Try to fix GCC error about invalid use of const_cast in const version of ↵Alexey Samsonov2014-10-201-1/+1
| | | | | | ErrorOr::get() llvm-svn: 220233
* Constify getELFDynamicSymbolIterators standalone function. NFC.Alexey Samsonov2014-10-201-1/+1
| | | | llvm-svn: 220232
* Add const version of OwningBinary::getBinaryAlexey Samsonov2014-10-201-0/+6
| | | | llvm-svn: 220231
* Be more specific about return type of MachOUniversalBinary::getObjectForArchAlexey Samsonov2014-10-202-6/+4
| | | | llvm-svn: 220230
* Constify input argument of RelocVisitor and DWARFContext constructors. NFC.Alexey Samsonov2014-10-205-6/+6
| | | | llvm-svn: 220228
* Teach Lit to catch OSError exceptions when creating a process during theDan Liew2014-10-201-7/+10
| | | | | | | | | execution of a shell command. This can happen for example if the ``RUN:`` line calls a python script which can work correctly under Linux/OSX but will not work under Windows. A more useful error message is now shown rather than an unhelpful backtrace. llvm-svn: 220227
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