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* Only set branch weight during sample pgo annotation when max_weight of the ↵Dehao Chen2016-09-192-19/+20
| | | | | | | | | | | | | | branch is non-zero. Otherwise use default static profile to set branch probability. Summary: It does not make sense to set equal weights for all unkown branches as we have static branch prediction available. Reviewers: dnovillo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D24732 llvm-svn: 281912
* Use call target count to derive the call instruction weightDehao Chen2016-09-193-4/+21
| | | | | | | | | | | | Summary: The call target count profile is directly derived from LBR branch->target data. This is more reliable than instruction frequency profiles that could be moved across basic block boundaries. This patches uses call target count profile to annotate call instructions. Reviewers: davidxl, dnovillo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D24410 llvm-svn: 281911
* [asan] Support dynamic shadow address instrumentationEtienne Bergeron2016-09-192-7/+81
| | | | | | | | | | | | | | | | | | | Summary: This patch is adding the support for a shadow memory with dynamically allocated address range. The compiler-rt needs to export a symbol containing the shadow memory range. This is required to support ASAN on windows 64-bits. Reviewers: kcc, rnk, vitalybuka Subscribers: kubabrecka, dberris, llvm-commits, chrisha Differential Revision: https://reviews.llvm.org/D23354 llvm-svn: 281908
* [Support] Add StringRef::withNullAsEmpty()Zachary Turner2016-09-191-0/+4
| | | | | | | | | | | When porting large bodies of code from using const char* to StringRef, it is helpful to be able to treat nullptr as an empty string, since that it is often what it is used to indicate in C-style code. Differential Revision: https://reviews.llvm.org/D24697 llvm-svn: 281906
* Revert r281841, it does not work on Windows (PR30443).Nico Weber2016-09-191-722/+0
| | | | llvm-svn: 281905
* [AMDGPU] Refactor VOPC instruction TD definitionsValery Pykhtin2016-09-196-648/+1118
| | | | | | Differential Revision: https://reviews.llvm.org/D24546 llvm-svn: 281903
* [AArch64] Fix encoding for lsl #12 in add/sub immediatesDiana Picus2016-09-194-12/+27
| | | | | | | | | | | Whenever an add/sub immediate needs a fixup, we set that immediate field to zero, which is correct, but we also set the shift bits to zero, which is not true for instructions that use lsl #12. This patch makes sure that if lsl #12 was used, it will appear in the encoding of the instruction. Differential Revision: https://reviews.llvm.org/D23930 llvm-svn: 281898
* [AMDGPU] Fix s_branch with -1 offsetSam Kolton2016-09-192-5/+9
| | | | | | | | | | | | | | | | | | | Summary: In case s_branch instruction target is itself backend should emit offset -1 but instead it emit 0. ''' label: s_branch label // should emit [0xff,0xff,0x82,0xbf] ''' Tom, Matt: why are we adjusting fixup values in applyFixup() method instead of processFixup()? processFixup() is calling adjustFixupValue() but does nothing with its result. Reviewers: vpykhtin, artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl Differential Revision: https://reviews.llvm.org/D24671 llvm-svn: 281896
* Add @llvm.dbg.value entries for the phi node created by -mem2regKeith Walker2016-09-194-0/+134
| | | | | | | | | | | | | | | | | | | | | | | When phi nodes are created in the -mem2reg phase, the @llvm.dbg.declare entries are converted to @llvm.dbg.value entries at the place where the store instructions existed. However no entry is created to describe the resulting value of the phi node. The effect of this is especially noticeable in for loops which have a constant for the intial value; the loop control variable's location would be described as the intial constant value in the loop body once the -mem2reg optimization phase was run. This change adds the creation of the @llvm.dbg.value entries to describe variables whose location is the result of a phi node created in -mem2reg. Also when the phi node is finally lowered to a machine instruction it is important that the lowered "load" instruction is placed before the associated DEBUG_VALUE entry describing the value loaded. Differential Revision: https://reviews.llvm.org/D23715 llvm-svn: 281895
* [Thumb] Set correct initial mapping symbol for big-endian thumbOliver Stannard2016-09-192-1/+11
| | | | | | | | | | The initial mapping symbol state is set from the triple, but we only checked for the little-endian thumb triple, so could end up with an ARM mapping symbol for big-endian thumb. Differential Revision: https://reviews.llvm.org/D24553 llvm-svn: 281894
* ARM: check alignment before transforming ldr -> ldm (or similar).Tim Northover2016-09-193-8/+41
| | | | | | | | | ldm and stm instructions always require 4-byte alignment on the pointer, but we weren't checking this before trying to reduce code-size by replacing a post-indexed load/store with them. Unfortunately, we were also dropping this incormation in DAG ISel too, but that's easy enough to fix. llvm-svn: 281893
* [X86 Codegen Test] Divided masked_memop into several files. NFC.Elena Demikhovsky2016-09-193-9370/+436
| | | | | | The masked_memop.ll became huge. I extracted AVX-512 specific tests into separate files. llvm-svn: 281892
* [SimplifyCFG] Update (AND) IR flags when CSE'ing instructionsJames Molloy2016-09-192-2/+60
| | | | | | | | We were updating metadata but not IR flags. Because we pick an arbitrary instruction to be the CSE candidate, it comes down to luck (50% or less chance) if this results in broken codegen or not, which is why PR30373 which is actually not the fault of the commit it was bisected down to. Fixes PR30373. llvm-svn: 281889
* [X86,AVX-512] Use INSERT_SUBREG instead of SUBREG_TO_REG when the input is ↵Craig Topper2016-09-198-130/+146
| | | | | | | | not the output of an instruction. SUBREG_TO_REG is supposed to indicate that the super register has been zeroed, but we can't prove that if we don't know where it came from. llvm-svn: 281885
* [AVX-512] Add support for lowering fp_to_f16 and f16_to_fp when VLX is ↵Craig Topper2016-09-194-1633/+891
| | | | | | | | supported regardless of whether F16C is also supported. Still need to add support for lowering using AVX512F when neither VLX or F16C is supported. llvm-svn: 281884
* [llvm-cov] Emit a link to some documentationVedant Kumar2016-09-191-0/+7
| | | | llvm-svn: 281883
* [llvm-cov] Delete the NonCodeLines field, it was always deadVedant Kumar2016-09-199-42/+26
| | | | llvm-svn: 281882
* [XRay] ARM 32-bit no-Thumb support in LLVMDean Michael Berris2016-09-1917-63/+328
| | | | | | | | | | | | This is a port of XRay to ARM 32-bit, without Thumb support yet. The XRay instrumentation support is moving up to AsmPrinter. This is one of 3 commits to different repositories of XRay ARM port. The other 2 are: https://reviews.llvm.org/D23932 (Clang test) https://reviews.llvm.org/D23933 (compiler-rt) Differential Revision: https://reviews.llvm.org/D23931 llvm-svn: 281878
* [llvm-cov] Teach the coverage exporter about instantiation coverageVedant Kumar2016-09-197-16/+32
| | | | | | | While we're at it, re-use the logic from CoverageReport to compute summaries. llvm-svn: 281877
* [llvm-cov] Make a helper method static for re-use (NFC)Vedant Kumar2016-09-193-8/+9
| | | | llvm-svn: 281876
* [llvm-cov] Track function and instantiation coverage separatelyVedant Kumar2016-09-198-19/+95
| | | | | | | | | | | | | | | | | | | | These are distinct statistics which are useful to look at separately. Example: say you have a template function "foo" with 5 instantiations and only 3 of them are covered. Then this contributes (1/1) to the total function coverage and (3/5) to the total instantiation coverage. I.e, the old "Function Coverage" column has been renamed to "Instantiation Coverage", and the new "Function Coverage" aggregates information from the various instantiations of a function. One benefit of making this switch is that the Line and Region coverage columns will start making sense. Let's continue the example and assume that the 5 instantiations of "foo" cover {2, 4, 6, 8, 10} out of 10 lines respectively. The new line coverage for "foo" is (10/10), not (30/50). The old scenario got confusing because we'd report that there were more lines in a file than what was actually possible. llvm-svn: 281875
* [llvm-cov] Don't recompute the 'Covered' field from *CoverageInfo (NFC)Vedant Kumar2016-09-191-6/+5
| | | | llvm-svn: 281874
* [llvm-cov] Make 'adjustColumnWidths' do less workVedant Kumar2016-09-191-12/+23
| | | | | | | | | | | | This drops some redundant calls to get{UniqueSourceFiles, CoveredFunctions}. We can figure out the right column widths without re-doing this expensive work. This isn't NFC, but I don't want to check in another binary *.covmapping file with long filenames in it. I tested this locally on a project with some long filenames (FileCheck). llvm-svn: 281873
* [llvm-cov] Drop another redundant 'No.' suffixVedant Kumar2016-09-192-2/+2
| | | | llvm-svn: 281872
* [utils] Delete the 'check-coverage-regressions' scriptVedant Kumar2016-09-191-139/+0
| | | | | | | | | In practice, it's way too noisy. It's also a maintenance burden, since we apparently can't add tests for it without breaking some Windows setups (see: D22692). llvm-svn: 281871
* Handle Invoke during sample profiler annotation: make it inlinable.Dehao Chen2016-09-183-23/+82
| | | | | | | | | | | | Summary: Previously we reline on inst-combine to remove inlinable invoke instructions. This causes trouble because a few extra optimizations are schedule early that could introduce too much CFG change (e.g. simplifycfg removes too much control flow). This patch handles invoke instruction in-place during sample profile annotation, so that we do not rely on instcombine to remove those invoke instructions. Reviewers: davidxl, dnovillo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D24409 llvm-svn: 281870
* Extend title underlineXinliang David Li2016-09-181-1/+1
| | | | llvm-svn: 281869
* [AVX-512] Don't lower CVTPD2PS intrinsics to ISD::FP_ROUND with an X86 ↵Craig Topper2016-09-183-4/+30
| | | | | | | | rounding mode encoding in the second operand. This immediate should only be 0 or 1 and indicates if the truncation loses precision. Also enhance an assert in SelectionDAG::getNode to flag this sort of problem in the future. llvm-svn: 281868
* [AVX-512] Stop lowering avx512_mask_sqrt intrinsics to ISD:FSQRT with a ↵Craig Topper2016-09-181-2/+2
| | | | | | second operand containing an X86 specific rounding mode encoding that doesn't belong. llvm-svn: 281867
* [libFuzzer] add -print_coverage=1 flag to print coverage directly from ↵Kostya Serebryany2016-09-188-10/+45
| | | | | | libFuzzer llvm-svn: 281866
* Fix covered-switch-default warningSimon Pilgrim2016-09-181-5/+4
| | | | llvm-svn: 281865
* [CostModel][X86] Added scalar float op costsSimon Pilgrim2016-09-181-252/+340
| | | | llvm-svn: 281864
* Rename testsSimon Pilgrim2016-09-181-18/+18
| | | | llvm-svn: 281863
* [X86] Fix typo in comment. NFCCraig Topper2016-09-181-1/+1
| | | | llvm-svn: 281862
* [AVX-512] Add memory load patterns for the legacy SSE scalar fp to integer ↵Craig Topper2016-09-181-1/+16
| | | | | | conversion intrinsics to be consistent across all intruction sets. llvm-svn: 281861
* [AVX-512] Remove COPY_TO_REGCLASS from a few patterns that already had the ↵Craig Topper2016-09-181-8/+8
| | | | | | correct register class. llvm-svn: 281860
* Fix built bot failureXinliang David Li2016-09-181-1/+1
| | | | llvm-svn: 281859
* [Profile] Implement select instruction instrumentation in IR PGOXinliang David Li2016-09-187-11/+241
| | | | | | Differential Revision: http://reviews.llvm.org/D23727 llvm-svn: 281858
* [Loop Vectorizer] Consecutive memory access - fixed and simplifiedElena Demikhovsky2016-09-184-86/+53
| | | | | | | | | Amended consecutive memory access detection in Loop Vectorizer. Load/Store were not handled properly without preceding GEP instruction. Differential Revision: https://reviews.llvm.org/D20789 llvm-svn: 281853
* [X86][SSE] Improve recognition of uitofp conversions that can be performed ↵Simon Pilgrim2016-09-186-495/+112
| | | | | | | | | | | | | | as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
* [Loop vectorizer] Simplified GEP cloning. NFC.Elena Demikhovsky2016-09-181-35/+26
| | | | | | | | | Simplified GEP cloning in vectorizeMemoryInstruction(). Added an assertion that checks consecutive GEP, which should have only one loop-variant operand. Differential Revision: https://reviews.llvm.org/D24557 llvm-svn: 281851
* Change the order of the splitted store from high - low to low - high.Wei Mi2016-09-182-6/+6
| | | | | | | It is a trivial change which could make the testcase easier to be reused for the store splitting in CodeGenPrepare. llvm-svn: 281846
* [libFuzzer] use 'if guard' instead of 'if guard >= 0' with trace-pc; change ↵Kostya Serebryany2016-09-183-47/+47
| | | | | | the guard type to intptr_t; use separate array for 8-bit counters llvm-svn: 281845
* [llvm-objump] Simplify the code. NFCI.Davide Italiano2016-09-181-23/+12
| | | | llvm-svn: 281844
* [lib/LTO] Try harder to reduce code duplication. NFCI.Davide Italiano2016-09-171-13/+14
| | | | llvm-svn: 281843
* [X86][SSE] Added vector udiv combine testsSimon Pilgrim2016-09-171-0/+199
| | | | llvm-svn: 281842
* [X86][SSE] Added vector fcopysign combine testsSimon Pilgrim2016-09-171-0/+722
| | | | | | Also demonstrating the poor lowering of fcopysign... llvm-svn: 281841
* [ThinLTO] Ensure anonymous globals renamed even at -O0Teresa Johnson2016-09-172-1/+10
| | | | | | | | | | | | | | | | | | | | | | Summary: This fixes an issue when files are compiled with -flto=thin at default -O0. We need to rename anonymous globals before attempting to write the module summary because all values need names for the summary. This was happening at -O1 and above, but not before the early exit when constructing the pipeline for -O0. Also add an internal -prepare-for-thinlto option to enable this to be tested via opt. Fixes PR30419. Reviewers: mehdi_amini Subscribers: probinson, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D24701 llvm-svn: 281840
* [X86][SSE] Added vector mul combine testsSimon Pilgrim2016-09-171-0/+249
| | | | llvm-svn: 281839
* [X86][SSE] Improve target shuffle mask extractionSimon Pilgrim2016-09-173-22/+16
| | | | | | Add ability to extract vXi64 'vzext_movl' masks on 32-bit targets llvm-svn: 281834
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