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* Reapply r141605 with fixes for appropriate handling of reserved section numbersNick Lewycky2011-10-111-17/+50
| | | | | | in st_shndx fields. llvm-svn: 141639
* Add support for .symtab_shnidx. Unfortunately, doing this required breaking aNick Lewycky2011-10-112-9/+48
| | | | | | | layer of abstraction around SymbolRef where you can read its private SymbolPimpl member. llvm-svn: 141636
* Add experimental -enable-lsr-phielim option.Andrew Trick2011-10-111-0/+22
| | | | | | | I'm not sure we will need it in the long run, but the option is currently useful for checking if the output of LSR is "clean". llvm-svn: 141634
* Move replaceCongruentIVs into SCEVExapander and bias toward "expanded"Andrew Trick2011-10-114-88/+129
| | | | | | | | | | | IVs. Indvars previously chose randomly between congruent IVs. Now it will bias the decision toward IVs that SCEVExpander likes to create. This was not done to fix any problem, it's just a welcome side effect of factoring code. llvm-svn: 141633
* Test cases for 64-bit load and store instructions.Akira Hatanaka2011-10-112-0/+215
| | | | llvm-svn: 141631
* Added a testcase for r141599, rdar://problem/10063881.Lang Hames2011-10-111-0/+20
| | | | llvm-svn: 141628
* Make changes necessary for supporting floating point load and store instructionsAkira Hatanaka2011-10-114-23/+50
| | | | | | | that have 64-bit pointers or access the 32 x 64-bit floating pointer register file. Update functions in MipsInstrInfo.cpp too. llvm-svn: 141623
* Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo().Jakob Stoklund Olesen2011-10-112-30/+44
| | | | | | | | | | | The VMOVS widening needs to look at the implicit COPY operands. Trying to dig out the COPY instruction from an iterator in copyPhysReg() is the wrong approach. The expandPostRAPseudo() hook gets to look at COPY instructions before they are converted to copyPhysReg() calls. llvm-svn: 141619
* Modify lowering of GlobalAddress so that correct code is emitted when target isAkira Hatanaka2011-10-113-14/+23
| | | | | | Mips64. llvm-svn: 141618
* Fixed natural stack alignment for Linux x86-32. Thanks Eli.Lang Hames2011-10-111-1/+1
| | | | llvm-svn: 141616
* Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too.Akira Hatanaka2011-10-111-7/+10
| | | | llvm-svn: 141615
* Revert r141605 as it broke tests for llvm-nm.Nick Lewycky2011-10-111-34/+13
| | | | llvm-svn: 141614
* Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot.Akira Hatanaka2011-10-112-17/+24
| | | | llvm-svn: 141613
* Add definitions of 64-bit loads and stores. Add a patterns for unalignedAkira Hatanaka2011-10-113-1/+38
| | | | | | zextloadi32 for which there is no corresponding pseudo or real instruction. llvm-svn: 141608
* Add testcase for PR11107.Bill Wendling2011-10-111-0/+49
| | | | llvm-svn: 141607
* Make it possible to use the linker without destroying the source module. ↵Tanya Lattner2011-10-115-38/+73
| | | | | | | | | | | | | | This is so the source module can be linked to multiple other destination modules. For all that used LinkModules() before, they will continue to destroy the source module as before. This line, and those below, will be ignored-- M include/llvm/Linker.h M tools/bugpoint/Miscompilation.cpp M tools/bugpoint/BugDriver.cpp M tools/llvm-link/llvm-link.cpp M lib/Linker/LinkModules.cpp llvm-svn: 141606
* Add support for reading many-section ELF files.Nick Lewycky2011-10-111-13/+34
| | | | | | | If you want to tackle adding the testcase, let me know. It's a 4.2MB ELF file and I'll be happy to mail it to you. llvm-svn: 141605
* Change definitions of classes LoadM and StoreM in preparation for adding supportAkira Hatanaka2011-10-112-20/+65
| | | | | | | for 64-bit load and store instructions. Add definitions of 64-bit memory operand and 16-bit immediate operand. llvm-svn: 141603
* Simplify check that optional def is there and is CPSR.Bill Wendling2011-10-111-5/+4
| | | | llvm-svn: 141602
* Add a natural stack alignment field to TargetData, and prevent InstCombine fromLang Hames2011-10-108-14/+45
| | | | | | | | | | | | | | promoting allocas to preferred alignments that exceed the natural alignment. This avoids some potentially expensive dynamic stack realignments. The natural stack alignment is set in target data strings via the "S<size>" option. Size is in bits and must be a multiple of 8. The natural stack alignment defaults to "unspecified" (represented by a zero value), and the "unspecified" value does not prevent any alignment promotions. Target maintainers that care about avoiding promotions should explicitly add the "S<size>" option to their target data strings. llvm-svn: 141599
* Fix warning.Michael J. Spencer2011-10-101-2/+2
| | | | llvm-svn: 141597
* Revert r141569 and r141576.Devang Patel2011-10-106-88/+62
| | | | llvm-svn: 141594
* Simplify operand Kind checks a bit.Jim Grosbach2011-10-101-20/+20
| | | | llvm-svn: 141592
* Reapply r141365 now that PR11107 is fixed.Bill Wendling2011-10-106-7/+177
| | | | llvm-svn: 141591
* Add a name to sub-operand for clarity.Jim Grosbach2011-10-101-1/+1
| | | | llvm-svn: 141590
* If the CPSR is defined by a copy, then we don't want to merge it into an ITBill Wendling2011-10-101-0/+22
| | | | | | | | | | | | | | | | | | | | | block. E.g., if we have: movs r1, r1 rsb r1, 0 movs r2, r2 rsb r2, 0 we don't want this to be converted to: movs r1, r1 movs r2, r2 itt mi rsb r1, 0 rsb r2, 0 PR11107 & <rdar://problem/10259534> llvm-svn: 141589
* Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. ↵Eli Friedman2011-10-102-12/+14
| | | | | | Fixes PR11102. llvm-svn: 141585
* Object: add getSectionAlignment.Michael J. Spencer2011-10-105-0/+43
| | | | llvm-svn: 141581
* Add support for dumping section headers to llvm-objdump. This uses the sameNick Lewycky2011-10-103-1/+117
| | | | | | | | flags as binutils objdump but the output is different, not just in format but also showing different sections. Compare its results against readelf, not objdump. llvm-svn: 141579
* Give targets a chance to expand even standard pseudos.Jakob Stoklund Olesen2011-10-101-4/+12
| | | | | | | | | | | Allow targets to expand COPY and other standard pseudo-instructions before they are expanded with copyPhysReg(). This allows the target to examine the COPY instruction for extra operands indicating it can be widened to a preferable super-register copy. See the ARM -widen-vmovs option. llvm-svn: 141578
* If loop header is also loop exiting block then it may not be safe to hoist ↵Devang Patel2011-10-103-64/+5
| | | | | | instructions. llvm-svn: 141576
* Emit full ED initializers even for pseudo-instructions.Jakob Stoklund Olesen2011-10-101-14/+14
| | | | | | This should unbreak the picky buildbots. llvm-svn: 141575
* Allow stat += 0 without activating the stat.Andrew Trick2011-10-101-0/+2
| | | | | | | For me, this is a nice convenience. We generally want grep to match stats output only when the event has occurred. llvm-svn: 141574
* whitespaceAndrew Trick2011-10-101-8/+8
| | | | llvm-svn: 141572
* X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy ↵Benjamin Kramer2011-10-101-0/+5
| | | | | | bridge. llvm-svn: 141571
* Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because theNadav Rotem2011-10-102-15/+7
| | | | | | instruction set has no 64-bit SRA support. llvm-svn: 141570
* Add dominance check for the instruction being hoisted.Devang Patel2011-10-104-3/+88
| | | | | | | For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. llvm-svn: 141569
* Mark the standard pseudos as isPseudo = 1.Jakob Stoklund Olesen2011-10-101-1/+1
| | | | | | | | | | | The difference between isPseudo and isCodeGenOnly is a bit murky, but isCodeGenOnly should eventually go away. It is used for instructions that are clones of real instructions with slightly different properties. The standard pseudo-instructions never mirror real instructions, so they are definitely in the isPseudo category. llvm-svn: 141567
* The Mips specific function for instruction cache invalidation cannot beBruno Cardoso Lopes2011-10-101-34/+5
| | | | | | | | | compiled on mips32r1 processors because it uses synci and rdhwr instructions which are supported only on mips32r2, so I replaced this function with the call to function cacheflush which works for both mips32r1 and mips32r2. Patch by Sasa Stankovic llvm-svn: 141564
* X86: Add patterns for the movbe instruction (mov + bswap, only available on ↵Benjamin Kramer2011-10-104-12/+49
| | | | | | atom) llvm-svn: 141563
* Insert dummy ED table entries for pseudo-instructions.Jakob Stoklund Olesen2011-10-102-3/+7
| | | | | | | | | | The table is indexed by opcode, so simply removing pseudo-instructions creates a wrong mapping from opcode to table entry. Add a test case for xorps which has a very high opcode that exposes this problem. llvm-svn: 141562
* Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame toBill Wendling2011-10-106-177/+7
| | | | | | hang, and possibly SPEC/CINT2006/464_h264ref. llvm-svn: 141560
* MCAtom extending methods need to extend the range of the atom as well.Owen Anderson2011-10-102-9/+20
| | | | llvm-svn: 141557
* Mark the llvm.eh.sjlj.functioncontext intrinsic as reading memory so that fastBill Wendling2011-10-101-4/+4
| | | | | | isel doesn't ignore it. llvm-svn: 141548
* llvm-objdump: Take ownership of MCInstrInfos.Benjamin Kramer2011-10-102-8/+2
| | | | llvm-svn: 141535
* llvm-nm: Don't leak bitcode buffers.Benjamin Kramer2011-10-101-2/+2
| | | | llvm-svn: 141534
* XFAIL tblgen tests on leak checkers.Benjamin Kramer2011-10-103-0/+3
| | | | llvm-svn: 141533
* When getting the number of bits necessary for addressing modeBill Wendling2011-10-102-3/+12
| | | | | | | | ARMII::AddrModeT1_s, we need to take into account that if the frame register is ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of bits is 5. llvm-svn: 141529
* Put a bunch of calls to ToggleFeature behind proper if statements.Craig Topper2011-10-101-17/+42
| | | | llvm-svn: 141527
* Fix a regression from r138445. If we're loading from the frame/base pointerChad Rosier2011-10-101-0/+1
| | | | | | | | the tADDrSPi instruction can't be used. Make sure we're updating the opcode to tADDi3 in all cases. rdar://10254707 llvm-svn: 141523
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