When getting the number of bits necessary for addressing mode

ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.

llvm-svn: 141529

2 files changed, 12 insertions, 3 deletions

diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 7c42342229a..0c8480d9ef2 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -1109,11 +1109,20 @@ bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
   case ARMII::AddrMode3:
     NumBits = 8;
     break;
-  case ARMII::AddrModeT1_s:
-    NumBits = 5;
+  case ARMII::AddrModeT1_s: {
+    const MachineBasicBlock &MBB = *MI->getParent();
+    const MachineFunction &MF = *MBB.getParent();
+    unsigned FrameReg = ARM::SP;
+    if (MF.getFrameInfo()->hasVarSizedObjects())
+      // There are alloca()'s in this function, must reference off the frame
+      // pointer or base pointer instead.
+      FrameReg = (!hasBasePointer(MF) ?BasePtr : getFrameRegister(MF));
+
+    NumBits = (FrameReg == ARM::SP) ? 8 : 5;
     Scale = 4;
     isSigned = false;
     break;
+  }
   default:
     llvm_unreachable("Unsupported addressing mode!");
     break;
diff --git a/llvm/test/CodeGen/Thumb/vargs.ll b/llvm/test/CodeGen/Thumb/vargs.ll
index c2ba208e4ae..16a9c4442d8 100644
--- a/llvm/test/CodeGen/Thumb/vargs.ll
+++ b/llvm/test/CodeGen/Thumb/vargs.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -march=thumb
-; RUN: llc < %s -mtriple=thumb-linux | grep pop | count 2
+; RUN: llc < %s -mtriple=thumb-linux | grep pop | count 1
 ; RUN: llc < %s -mtriple=thumb-darwin | grep pop | count 2
 
 @str = internal constant [4 x i8] c"%d\0A\00"           ; <[4 x i8]*> [#uses=1]