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* Move the machine operand MC encoding patterns to the parent classes.Bill Wendling2010-11-012-41/+36
| | | | llvm-svn: 117956
* Use ARM-style comments.Bill Wendling2010-11-011-62/+61
| | | | llvm-svn: 117955
* When folding away a (shl (shr)) pair, we need to check that the bits that ↵Owen Anderson2010-11-012-1/+21
| | | | | | | | will BECOME the low bits are zero, not that the current low bits are zero. Fixes <rdar://problem/8606771>. llvm-svn: 117953
* use our fancy new MnemonicAlias mechanism to remove a bunch of hacksChris Lattner2010-11-012-51/+16
| | | | | | from X86AsmParser.cpp llvm-svn: 117952
* When we look at instructions to convert to setting the 's' flag, we need to lookBill Wendling2010-11-014-18/+23
| | | | | | | | | | | | | | | | | | | | | | | | at more than those which define CPSR. You can have this situation: (1) subs ... (2) sub r6, r5, r4 (3) movge ... (4) cmp r6, 0 (5) movge ... We cannot convert (2) to "subs" because (3) is using the CPSR set by (1). There's an analogous situation here: (1) sub r1, r2, r3 (2) sub r4, r5, r6 (3) cmp r4, ... (5) movge ... (6) cmp r1, ... (7) movge ... We cannot convert (1) to "subs" because of the intervening use of CPSR. llvm-svn: 117950
* Don't assign new registers created during a split to the same stack slot, butJakob Stoklund Olesen2010-11-013-16/+3
| | | | | | give them individual stack slots once the are actually spilled. llvm-svn: 117945
* Add basic LiveStacks verification.Jakob Stoklund Olesen2010-11-011-0/+20
| | | | | | | When an instruction refers to a spill slot with a LiveStacks entry, check that the spill slot is live at the instruction. llvm-svn: 117944
* Use ARM-style comment syntax.Owen Anderson2010-11-0118-626/+626
| | | | llvm-svn: 117941
* NEON does not support truncating vector stores. Radar 8598391.Bob Wilson2010-11-012-0/+14
| | | | llvm-svn: 117940
* Covert this test to .s form.Owen Anderson2010-11-012-103/+19
| | | | llvm-svn: 117939
* Convert this test to .s form.Owen Anderson2010-11-012-538/+108
| | | | llvm-svn: 117938
* Covert this test to .s form.Owen Anderson2010-11-012-215/+46
| | | | llvm-svn: 117937
* Add FIXME.Jim Grosbach2010-11-011-0/+1
| | | | llvm-svn: 117936
* Covert this test to .s form.Owen Anderson2010-11-012-449/+98
| | | | llvm-svn: 117935
* Fix test.Rafael Espindola2010-11-011-1/+1
| | | | llvm-svn: 117932
* Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gatesJim Grosbach2010-11-012-20/+22
| | | | | | | codegen using the patterns; the latter gates the assembler recognizing the instruction. llvm-svn: 117931
* Write the line info to .debug_line.Rafael Espindola2010-11-012-0/+31
| | | | llvm-svn: 117930
* Mark ARM subtarget features that are available for the assembler.Jim Grosbach2010-11-0123-36/+42
| | | | llvm-svn: 117929
* trailing whitespaceJim Grosbach2010-11-011-5/+5
| | | | llvm-svn: 117927
* Move EmitInstruction to MCObjectStreamer so that ELF and MachO can share it.Rafael Espindola2010-11-015-69/+50
| | | | llvm-svn: 117925
* The T2 extract/pack instructions are only valid in Thumb2 mode. Mark theJim Grosbach2010-11-011-12/+14
| | | | | | patterns as such llvm-svn: 117923
* Add support for .value.Rafael Espindola2010-11-012-0/+6
| | | | llvm-svn: 117922
* Implement .weakref.Rafael Espindola2010-11-0112-6/+372
| | | | llvm-svn: 117911
* Move instruction encoding bits into the parent class and remove the temporaryBill Wendling2010-11-012-273/+224
| | | | | | | *_Encode classes. These instructions are the only ones which use those classes, so a subclass isn't necessary. llvm-svn: 117906
* More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when theBill Wendling2010-11-012-4/+5
| | | | | | peephole optimizer is disabled. That's not good at all. llvm-svn: 117905
* The testcase is now XFAILed. Sorry about the breakage.Bill Wendling2010-11-011-0/+2
| | | | llvm-svn: 117904
* Disable because peephole is disabled.Bill Wendling2010-11-011-0/+1
| | | | llvm-svn: 117903
* "mov[zs]x (mem), GR16" are not ambiguous: the memChris Lattner2010-11-012-0/+12
| | | | | | must be 8 bits. Support this memory form. llvm-svn: 117902
* Implement enough of the missing instalias support to getChris Lattner2010-11-016-16/+96
| | | | | | | | | | | | | | | | | | aliases installed and working. They now work when the matched pattern and the result instruction have exactly the same operand list. This is now enough for us to define proper aliases for movzx and movsx, implementing rdar://8017633 and PR7459. Note that we do not accept instructions like: movzx 0(%rsp), %rsi GAS accepts this instruction, but it doesn't make any sense because we don't know the size of the memory operand. It could be 8/16/32 bits. llvm-svn: 117901
* Convert this test to .s form.Owen Anderson2010-11-012-697/+160
| | | | llvm-svn: 117900
* rename InstructionInfo -> MatchableInfo since it nowChris Lattner2010-11-011-65/+74
| | | | | | | | represents InstAliases as well. Rename isAssemblerInstruction -> Validate since that is what it does (modulo the ARM $lane hack). llvm-svn: 117899
* refactor initialization of InstructionInfo to be sharable betweenChris Lattner2010-11-011-27/+46
| | | | | | | instructions and InstAliases. Start creating InstructionInfo's for Aliases. llvm-svn: 117898
* make the asm matcher emitter reject instructions that have commentsChris Lattner2010-11-013-41/+32
| | | | | | | in their asmstring. Fix the two x86 "NOREX" instructions that have them. If these comments are important, the instlowering stuff can print them. llvm-svn: 117897
* refactor InstructionInfo to not have a pointer to CodeGenInstructionChris Lattner2010-11-011-88/+89
| | | | | | | member, and make isAssemblerInstruction() a method (pushing some code around inside it). llvm-svn: 117895
* define a new CodeGenInstAlias. It has an asmstring and operand list for now,Chris Lattner2010-11-013-1/+37
| | | | | | todo: the result field. llvm-svn: 117894
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-0113-301/+340
| | | | | | CodeGenInstruction into its own helper class. No functionality change. llvm-svn: 117893
* avoid needless throw/catch/rethrow, stringref'ize some simple stuff.Chris Lattner2010-11-013-10/+7
| | | | llvm-svn: 117892
* eliminate the old InstFormatName which is always "AsmString",Chris Lattner2010-11-015-15/+6
| | | | | | simplify CodeGenInstruction. No functionality change. llvm-svn: 117891
* all predicates on an MnemonicAlias must be AssemblerPredicates.Chris Lattner2010-11-011-6/+10
| | | | llvm-svn: 117890
* change the singleton register handling code to be based on Record*'sChris Lattner2010-11-011-48/+41
| | | | | | instead of strings, simplifying it. llvm-svn: 117889
* Give AsmMatcherInfo a CodeGenTarget, which simplifies a bunch ofChris Lattner2010-11-011-83/+92
| | | | | | | | | argument passing. Consolidate all SingletonRegister detection and handling into a new InstructionInfo::getSingletonRegisterForToken method instead of having it scattered about. No change in generated .inc files. llvm-svn: 117888
* move FlattenVariants out of AsmMatcherEmitter into a sharedChris Lattner2010-11-014-121/+98
| | | | | | | | CodeGenInstruction::FlattenAsmStringVariants method. Use it to simplify the code in AsmWriterInst, which now no longer needs to worry about variants. llvm-svn: 117886
* add a FIXME, $lane in ARM is an issue that needs to be resolved beforeChris Lattner2010-11-011-1/+2
| | | | | | this can start rejecting instructions. llvm-svn: 117885
* reject instructions that contain a \n in their asmstring. MarkChris Lattner2010-11-013-15/+23
| | | | | | | various X86 and ARM instructions that are bitten by this as isCodeGenOnly, as they are. llvm-svn: 117884
* Add a specialization for 'long', a hole in the set of fundamentalChandler Carruth2010-10-311-0/+14
| | | | | | | | | specializations provided here. This is a little annoying because its size changes from platform to platform. If possible, I may follow up with a patch that uses standard constants to simplify much of this, but assuming for now that was avoided for a reason. llvm-svn: 117880
* Revert r117876 for now, it's causing more testsuite failures.Eric Christopher2010-10-311-2/+0
| | | | llvm-svn: 117879
* Disable the peephole optimizer until 186.crafty on armv6 is fixed. This is whatBill Wendling2010-10-311-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | looks like is happening: Without the peephole optimizer: (1) sub r6, r6, #32 orr r12, r12, lr, lsl r9 orr r2, r2, r3, lsl r10 (x) cmp r6, #0 ldr r9, LCPI2_10 ldr r10, LCPI2_11 (2) sub r8, r8, #32 (a) movge r12, lr, lsr r6 (y) cmp r8, #0 LPC2_10: ldr lr, [pc, r10] (b) movge r2, r3, lsr r8 With the peephole optimizer: ldr r9, LCPI2_10 ldr r10, LCPI2_11 (1*) subs r6, r6, #32 (2*) subs r8, r8, #32 (a*) movge r12, lr, lsr r6 (b*) movge r2, r3, lsr r8 (1) is used by (x) for the conditional move at (a). (2) is used by (y) for the conditional move at (b). After the peephole optimizer, these the flags resulting from (1*) are ignored and only the flags from (2*) are considered for both conditional moves. llvm-svn: 117876
* Attach a GCModuleInfo to a MachineFunction.Nicolas Geoffray2010-10-313-4/+11
| | | | llvm-svn: 117867
* fix a crash on:Chris Lattner2010-10-311-1/+2
| | | | | | | | | | | | let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 { we now get: X86InstrCompiler.td:653:52: error: Expected class, def, defm, multiclass or let definition let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 { ^ llvm-svn: 117863
* fix the !eq operator in tblgen to return a bit instead of an int.Chris Lattner2010-10-315-17/+8
| | | | | | | | Use this to make the X86 and ARM targets set isCodeGenOnly=1 automatically for their instructions that have Format=Pseudo, resolving a hack in tblgen. llvm-svn: 117862
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