fix the !eq operator in tblgen to return a bit instead of an int.

Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862

5 files changed, 8 insertions, 17 deletions

diff --git a/llvm/docs/TableGenFundamentals.html b/llvm/docs/TableGenFundamentals.html
index 2f0c4ae6ec2..e9067b0e1ee 100644
--- a/llvm/docs/TableGenFundamentals.html
+++ b/llvm/docs/TableGenFundamentals.html
@@ -422,7 +422,7 @@ class.  This operation is analogous to $(foreach) in GNU make.</dd>
   <dd>'b' if the result of 'int' or 'bit' operator 'a' is nonzero,
       'c' otherwise.</dd>
 <dt><tt>!eq(a,b)</tt></dt>
-  <dd>Integer one if string a is equal to string b, zero otherwise.  This
+  <dd>'bit 1' if string a is equal to string b, 0 otherwise.  This
       only operates on string, int and bit objects.  Use !cast&lt;string&gt; to
       compare other types of objects.</dd>
 </dl>
diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td
index 91789dae608..aa5a45da75e 100644
--- a/llvm/lib/Target/ARM/ARMInstrFormats.td
+++ b/llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -203,6 +203,9 @@ class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
   Domain D = d;
   bit isUnaryDataProc = 0;
   bit canXformTo16Bit = 0;
+  
+  // If this is a pseudo instruction, mark it isCodeGenOnly.
+  let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
 
   // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
   let TSFlags{4-0}   = AM.Value;
diff --git a/llvm/lib/Target/X86/X86InstrFormats.td b/llvm/lib/Target/X86/X86InstrFormats.td
index ce85e3a49dc..a4403591084 100644
--- a/llvm/lib/Target/X86/X86InstrFormats.td
+++ b/llvm/lib/Target/X86/X86InstrFormats.td
@@ -125,6 +125,9 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
   dag InOperandList = ins;
   string AsmString = AsmStr;
 
+  // If this is a pseudo instruction, mark it isCodeGenOnly.
+  let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
+
   //
   // Attributes specific to X86 instructions...
   //
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 0fad96edde3..6ddccc21b7e 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -223,21 +223,6 @@ static bool IsAssemblerInstruction(StringRef Name,
   if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
     return false;
 
-  // Ignore pseudo ops.
-  //
-  // FIXME: This is a hack [for X86]; can we convert these instructions to set
-  // the "codegen only" bit instead?
-  if (const RecordVal *Form = CGI.TheDef->getValue("Form"))
-    if (Form->getValue()->getAsString() == "Pseudo")
-      return false;
-  
-  // FIXME: This is a hack [for ARM]; can we convert these instructions to set
-  // the "codegen only" bit instead?
-  if (const RecordVal *Form = CGI.TheDef->getValue("F"))
-    if (Form->getValue()->getAsString() == "Pseudo")
-      return false;
-  
-
   // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
   //
   // FIXME: This is a total hack.
diff --git a/llvm/utils/TableGen/TGParser.cpp b/llvm/utils/TableGen/TGParser.cpp
index 1f4b07b4bda..7bd2fbcd930 100644
--- a/llvm/utils/TableGen/TGParser.cpp
+++ b/llvm/utils/TableGen/TGParser.cpp
@@ -812,7 +812,7 @@ Init *TGParser::ParseOperation(Record *CurRec) {
     case tgtok::XSRA:    Code = BinOpInit::SRA;    Type = new IntRecTy(); break;
     case tgtok::XSRL:    Code = BinOpInit::SRL;    Type = new IntRecTy(); break;
     case tgtok::XSHL:    Code = BinOpInit::SHL;    Type = new IntRecTy(); break;
-    case tgtok::XEq:     Code = BinOpInit::EQ;     Type = new IntRecTy(); break;
+    case tgtok::XEq:     Code = BinOpInit::EQ;     Type = new BitRecTy(); break;
     case tgtok::XStrConcat:
       Code = BinOpInit::STRCONCAT;
       Type = new StringRecTy();