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* AArch64/ARM64: implement "mov $Rd, $Imm" aliases in TableGen.Tim Northover2014-05-123-58/+94
| | | | | | | | This is a slightly different approach to AArch64 (the base instruction definitions aren't quite right for that to work), but achieves the same thing and reduces C++ hackery in AsmParser. llvm-svn: 208605
* R600: Add mul24 intrinsicsMatt Arsenault2014-05-125-4/+35
| | | | llvm-svn: 208604
* Make SimplifyDemandedBits understand BUILD_PAIRMatt Arsenault2014-05-122-0/+61
| | | | llvm-svn: 208598
* [mips] Move disassembler test (test_2r_msa64) into correct folder.Matheus Almeida2014-05-122-6/+3
| | | | llvm-svn: 208594
* [mips] Move disassembler test (Mips MSA test_vec) into correct folder.Matheus Almeida2014-05-122-12/+9
| | | | llvm-svn: 208592
* [mips] Move disassembler tests (Mips MSA test_i*, test_mi10) into correct ↵Matheus Almeida2014-05-128-105/+92
| | | | | | folder. llvm-svn: 208590
* [mips] Move disassembler tests (Mips MSA test_elm*) into correct folder.Matheus Almeida2014-05-1210-50/+37
| | | | llvm-svn: 208589
* [mips] Move disassembler tests (Mips MSA test_lsa, test_dlsa) into correct ↵Matheus Almeida2014-05-124-18/+12
| | | | | | folder. llvm-svn: 208588
* [mips] Move disassembler test (Mips MSA test_ctrlregs) into correct folder.Matheus Almeida2014-05-122-38/+35
| | | | llvm-svn: 208587
* [mips] Move disassembler test (Mips MSA test_bit) into correct folder.Matheus Almeida2014-05-122-53/+50
| | | | llvm-svn: 208586
* [mips] Move disassembler tests (Mips MSA test_2r, test_2rf, test_3r, ↵Matheus Almeida2014-05-128-391/+379
| | | | | | | | test_3rf) into correct folder. llvm-svn: 208584
* Revert: r208582 - [mips][mips64r6] Add sel.s and sel.dDaniel Sanders2014-05-124-56/+4
| | | | | | Accidentally committed an unreviewed patch. Reverted it. llvm-svn: 208583
* [mips][mips64r6] Add sel.s and sel.dDaniel Sanders2014-05-124-4/+56
| | | | | | | | | | | | | Summary: Also use named constants for common opcode fields. Depends on D3669 Reviewers: jkolek, vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D3670 llvm-svn: 208582
* [ARM64-BE] Correct grammar mistake pointed out by Tobias.James Molloy2014-05-121-1/+1
| | | | llvm-svn: 208580
* [mips][mips64r6] Add d?div, d?mod, d?divu, d?moduDaniel Sanders2014-05-124-8/+44
| | | | | | | | | | | | Summary: Depends on D3668 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3669 llvm-svn: 208579
* [ARM64-BE] Add sphinx documentation for the ARM64 NEON implementation.James Molloy2014-05-126-0/+211
| | | | | | | There are some interesting decisions based on non-obvious rationale in the ARM64-BE NEON implementation - decent documentation is definitely required. llvm-svn: 208577
* [mips][mips64r6] Added mul/mulu/muh/muhuDaniel Sanders2014-05-127-9/+139
| | | | | | | | | | | | Summary: The 'mul' line of the test is temporarily commented out because it currently matches the MIPS32 mul instead of the MIPS32r6 mul. This line will be uncommented when we disable the MIPS32 mul on MIPS32r6. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3668 llvm-svn: 208576
* Move EmitDwarfAdvanceLineAddr and EmitDwarfAdvanceFrameAddr to the obj streamer.Rafael Espindola2014-05-125-40/+2
| | | | | | This lets us delete the MCAsmStreamer implementation. No functionality change. llvm-svn: 208570
* Pass a MCObjectStreamer instead of a MCStreamer when possible.Rafael Espindola2014-05-121-9/+9
| | | | | | No functionality change. llvm-svn: 208569
* Pass a MCObjectStreamer instead of a MCStreamer when possible.Rafael Espindola2014-05-122-11/+12
| | | | | | No functionality change. llvm-svn: 208567
* Silencing an MSVC warning about not all control paths returning a value ↵Aaron Ballman2014-05-121-0/+1
| | | | | | (even though the switch is fully covered). No functional change. llvm-svn: 208565
* ARM64: remove dead validation code from the AsmParser.Tim Northover2014-05-121-198/+0
| | | | | | | If this code triggers, any immediate has already been validated so it can't possibly trigger a diagnostic. llvm-svn: 208564
* ARM64: merge "extend" and "shift" addressing-mode enums.Tim Northover2014-05-126-330/+241
| | | | | | | | In terms of assembly, these have too much overlap to be neatly modelled as disjoint classes: in many cases "lsl" is an acceptable alternative to either "uxtw" or "uxtx". llvm-svn: 208563
* Move EH/Debug frame handling to the object streamer.Rafael Espindola2014-05-124-23/+27
| | | | | | | Now that the asm streamer doesn't use it, the MCStreamer doesn't need to know about it. llvm-svn: 208562
* Remove always true argument and unused field.Rafael Espindola2014-05-123-26/+9
| | | | llvm-svn: 208561
* Remove always true argument and field.Rafael Espindola2014-05-121-10/+7
| | | | llvm-svn: 208559
* Remove always true argument.Rafael Espindola2014-05-123-6/+5
| | | | llvm-svn: 208558
* Remove an always true argument.Rafael Espindola2014-05-125-7/+7
| | | | llvm-svn: 208557
* Remove write only field.Rafael Espindola2014-05-121-8/+0
| | | | llvm-svn: 208555
* Remove now empty method.Rafael Espindola2014-05-121-5/+0
| | | | llvm-svn: 208554
* Remove the always true UseCFI member.Rafael Espindola2014-05-121-90/+1
| | | | llvm-svn: 208553
* X86: Make sure that we have SSE4.1 before we generate insertps nodes.Benjamin Kramer2014-05-122-1/+11
| | | | | | PR19721. llvm-svn: 208552
* Remove the useCFI constructor argument to MCAsmStreamer.Rafael Espindola2014-05-121-5/+4
| | | | llvm-svn: 208551
* [mips] Marked up instructions added in MIPS32 and tested that IAS for ↵Daniel Sanders2014-05-126-48/+70
| | | | | | | | | | | | | | | | -mcpu=mips2 does not accept them Summary: To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are explicitly tested. Depends on D3695 Reviewers: vmedic Differential Revision: http://reviews.llvm.org/D3696 llvm-svn: 208549
* Remove MCUseCFI from TargetMachine.Rafael Espindola2014-05-122-8/+0
| | | | | | It was always true. llvm-svn: 208547
* [mips] Marked up instructions added in MIPS-V and tested that IAS for ↵Daniel Sanders2014-05-1220-16/+397
| | | | | | | | | | | | | | | | | | | | | | -mcpu=mips[1234] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-V that was available in MIPS32R2 Most of these instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. It happens because many of the MIPS V instructions have not been implemented. Depends on D3694 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3695 llvm-svn: 208546
* [mips] Fold FeatureBitCount into FeatureMips32 and FeatureMips64Daniel Sanders2014-05-128-25/+26
| | | | | | | | | | | | | | | | | | | | | Summary: DCL[ZO] are now correctly marked as being MIPS64 instructions. This has no effect on the CodeGen tests since expansion of i64 prevented their use anyway. The check for MIPS16 to prevent the use of CLZ no longer prevents DCLZ as well. This is not a functional change since DCLZ is still prohibited by being a MIPS64 instruction (MIPS16 is only compatible with MIPS32). No functional change Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3694 llvm-svn: 208544
* [mips] Fold FeatureSEInReg into FeatureMips32r2Daniel Sanders2014-05-127-26/+20
| | | | | | | | | | | | Summary: No functional change Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3693 llvm-svn: 208543
* [mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2Daniel Sanders2014-05-128-23/+24
| | | | | | | | | | | | | | | | | Summary: dsbh and dshd are not available on Mips32r2. No codegen test changes required since expansion of i64 prevented the use of these instructions anyway. Depends on D3690 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3692 llvm-svn: 208542
* [mips] Replace FeatureFPIdx with FeatureMips4_32r2Daniel Sanders2014-05-126-31/+40
| | | | | | | | | | | | | | | | | Summary: No functional change. The minor change to the MIPS16 code is in preparation for a patch that will handle 32-bit FPIdx instructions separately to 64-bit (because they were added in different revisions) Depends on D3677 Reviewers: rkotler, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3690 llvm-svn: 208541
* [ARM64] Add proper bounds checking/diagnostics to logical shiftsBradley Smith2014-05-124-26/+47
| | | | llvm-svn: 208540
* ARM: Implement big endian bit-conversion for NEON typeChristian Pirker2014-05-126-59/+537
| | | | llvm-svn: 208538
* X86ISelLowering.cpp:LowerINTRINSIC_W_CHAIN(): Prune impossible "default:" ↵NAKAMURA Takumi2014-05-121-3/+0
| | | | | | [-Wcovered-switch-default] llvm-svn: 208533
* Fix type of shuffle obtained from reordering with binary operationSerge Pavlov2014-05-122-1/+12
| | | | | | | | In transformation: BinOp(shuffle(v1,undef), shuffle(v2,undef)) -> shuffle(BinOp(v1, v2),undef) type of the undef argument must be same as type of BinOp. llvm-svn: 208531
* [ARM64] Add diagnostics for bitfield extract/insert instructionsBradley Smith2014-05-121-19/+54
| | | | | | | | Unfortunately, since ARM64 models all these instructions as aliases, the checks need to be done at the time the alias is seen rather than during instruction validation as AArch64 does it. llvm-svn: 208529
* [ARM64] Correct more bounds checks/diagnostics for arithmetic shift operandsBradley Smith2014-05-124-27/+19
| | | | llvm-svn: 208528
* [ARM64] Move register/register MOV handling into tablegen and improve ↵Bradley Smith2014-05-124-54/+26
| | | | | | diagnostics llvm-svn: 208527
* Fixed compilation issueElena Demikhovsky2014-05-121-0/+1
| | | | llvm-svn: 208524
* AVX-512: changes in intrinsicsElena Demikhovsky2014-05-126-431/+365
| | | | | | | | | 1) Changed gather and scatter intrinsics. Now they are aligned with GCC built-ins. There is no more non-masked form. Masked intrinsic receives -1 if all lanes are executed. 2) I changed the function that works with intrinsics inside X86ISelLowering.cpp. I put all intrinsics in one table. I did it for INTRINSICS_W_CHAIN and plan to put all intrinsics from WO_CHAIN set to the same table in order to avoid the long-long "switch". (I wanted to use static map initialization that allowed by C++11 but I wasn't able to compile it on VS2012). 3) I added gather/scatter prefetch intrinsics. 4) I fixed MRMm encoding for masked instructions. llvm-svn: 208522
* CodeGen: add parenthesis around complex expressionSaleem Abdulrasool2014-05-121-5/+5
| | | | | | Add missing parenthesis suggested by GCC. NFC. llvm-svn: 208519
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