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* The PowerPC VRSAVE register has been somewhat of an odd beast sinceBill Schmidt2012-10-103-6/+29
| | | | | | | | | | | | | | | | | the Altivec extensions were introduced. Its use is optional, and allows the compiler to communicate to the operating system which vector registers should be saved and restored during a context switch. In practice, this information is ignored by the various operating systems using the SVR4 ABI; the kernel saves and restores the entire register state. Setting the VRSAVE register is no longer performed by the AIX XL compilers, the IBM i compilers, or by GCC on Power Linux systems. It seems best to avoid this logic within LLVM as well. This patch avoids generating code to update and restore VRSAVE for the PowerPC SVR4 ABIs (32- and 64-bit). The code remains in place for the Darwin ABI. llvm-svn: 165656
* Add in support for expansion of all of the comparison operations to the ↵Micah Villmow2012-10-101-17/+62
| | | | | | | | | | absolute minimum required set. This allows a backend to expand any arbitrary set of comparisons as long as a minimum set is supported. The minimum set of required instructions is ISD::AND, ISD::OR, ISD::SETO(or ISD::SETOEQ) and ISD::SETUO(or ISD::SETUNE). Everything is expanded into one of two patterns: Pattern 1: (LHS CC1 RHS) Opc (LHS CC2 RHS) Pattern 2: (LHS CC1 LHS) Opc (RHS CC2 RHS) llvm-svn: 165655
* Revert r165652: "Remove unnecessary RTTI from the build."Sean Silva2012-10-104-0/+8
| | | | | | ... Apparently the RTTI is still necessary for some reason. llvm-svn: 165654
* Remove unnecessary RTTI from the build.Sean Silva2012-10-104-8/+0
| | | | llvm-svn: 165652
* tblgen: Compile TableGen without RTTI.Sean Silva2012-10-104-6/+0
| | | | | | TableGen no longer needs RTTI! llvm-svn: 165651
* tblgen: Move mini Type hierarchy to LLVM-style RTTI.Sean Silva2012-10-101-4/+22
| | | | llvm-svn: 165648
* tblgen: Use semantically correct RTTI functions.Sean Silva2012-10-1011-78/+57
| | | | | | Also, some minor cleanup. llvm-svn: 165647
* tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva2012-10-1015-192/+192
| | | | | | | | | | Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. llvm-svn: 165646
* tblgen: Put dyn_cast<> machinery in place for Init hierarchy.Sean Silva2012-10-101-20/+118
| | | | llvm-svn: 165645
* Add the testcase from pr13254 (the old scalarreply pass handles this wrong;Duncan Sands2012-10-101-0/+16
| | | | | | the new sroa pass handles it right). llvm-svn: 165644
* Remove dead variable.Bill Wendling2012-10-101-1/+0
| | | | llvm-svn: 165639
* Specify CPU model to avoid breaking ATOM buildsMichael Liao2012-10-102-4/+4
| | | | llvm-svn: 165638
* Remove unused argument.Bill Wendling2012-10-101-1/+1
| | | | llvm-svn: 165636
* docs: Propagate fix from r165632 to other docs.Sean Silva2012-10-101-2/+2
| | | | | | | There are only two other instances of using `.. code::` instead of `.. code-block::`. llvm-svn: 165633
* docs: Attempt to fix PR14053.Sean Silva2012-10-101-29/+29
| | | | | | | | | | | | | | | Hypothesis 1: use of `.. code::` directive instead of `.. code-block::` is causing Sphinx to discard the block. On my machine, `.. code::` renders fine. However, I don't think that `.. code::` is actually a legit Sphinx directive. I believe that on my machine Sphinx is falling back to just displaying it monospace with no syntax, whereas llvm.org's Sphinx is just discarding it. This is truly "remote debugging" since I can't reproduce this on my machine. It would be helpful to be able to see the llvm.org Sphinx build logs; if that's possible please let me know. llvm-svn: 165632
* Add support for FP_ROUND from v2f64 to v2f32Michael Liao2012-10-106-15/+121
| | | | | | | | | | - Due to the current matching vector elements constraints in ISD::FP_ROUND, rounding from v2f64 to v4f32 (after legalization from v2f32) is scalarized. Add a customized v2f32 widening to convert it into a target-specific X86ISD::VFPROUND to work around this constraints. llvm-svn: 165631
* Add alternative support for FP_ROUND from v2f32 to v2f64Michael Liao2012-10-104-90/+26
| | | | | | | | | | | - Due to the current matching vector elements constraints in ISD::FP_EXTEND, rounding from v2f32 to v2f64 is scalarized. Add a customized v2f32 widening to convert it into a target-specific X86ISD::VFPEXT to work around this constraints. This patch also reverts a previous attempt to fix this issue by recovering the scalarized ISD::FP_EXTEND pattern and thus significantly reduces the overhead of supporting non-power-2 vector FP extend. llvm-svn: 165625
* [CMake] check-all: Don't include check-llvm into check-all without ↵NAKAMURA Takumi2012-10-101-0/+5
| | | | | | | LLVM_BUILD_TOOLS. FIXME: Would you like to run llvm/unittests w/o LLVM_BUILD_TESTS regardless of LLVM_BUILD_TOOLS? llvm-svn: 165619
* [CMake] add_lit_testsuite: EXCLUDE_FROM_ALL excludes the test ${target} out ↵NAKAMURA Takumi2012-10-101-5/+8
| | | | | | of check-all. llvm-svn: 165618
* Fix for LDRB instruction:Stepan Dyatkovskiy2012-10-102-1/+25
| | | | | | | | | | | | | | | | | | | SDNode for LDRB_POST_IMM is invalid: number of registers added to SDNode fewer that described in .td. 7 ops is needed, but SDNode with only 6 is created. In more details: In ARMInstrInfo.td, in multiclass AI2_ldridx, in definition _POST_IMM, offset operand is defined as am2offset_imm. am2offset_imm is complex parameter type, and actually it consists from dummy register and imm itself. As I understood trick with dummy reg was made for AsmParser. In ARMISelLowering.cpp, this dummy register was not added to SDNode, and it cause crash in Peephole Optimizer pass. The problem fixed by setting up additional dummy reg when emitting LDRB_POST_IMM instruction. llvm-svn: 165617
* Issue description:Stepan Dyatkovskiy2012-10-105-12/+50
| | | | | | | | | | | | | | | | | | | | SchedulerDAGInstrs::buildSchedGraph ignores dependencies between FixedStack objects and byval parameters. So loading byval parameters from stack may be inserted *before* it will be stored, since these operations are treated as independent. Fix: Currently ARMTargetLowering::LowerFormalArguments saves byval registers with FixedStack MachinePointerInfo. To fix the problem we need to store byval registers with MachinePointerInfo referenced to first the "byval" parameter. Also commit adds two new fields to the InputArg structure: Function's argument index and InputArg's part offset in bytes relative to the start position of Function's argument. E.g.: If function's argument is 128 bit width and it was splitted onto 32 bit regs, then we got 4 InputArg structs with same arg index, but different offset values. llvm-svn: 165616
* Cleanup. Get rid of now dead code.Bill Wendling2012-10-102-36/+5
| | | | llvm-svn: 165613
* Remove the final bits of Attributes being declared in the AttributeBill Wendling2012-10-108-69/+61
| | | | | | | namespace. Use the attribute's enum value instead. No functionality change intended. llvm-svn: 165610
* My earlier "fix" for PBQP (see r165201) was incorrect. The real issue was thatLang Hames2012-10-101-2/+2
| | | | | | | | checkRegMaskInterference only initializes the bitmask on the first interference. This fixes PR14027 and (re)fixes PR13945. llvm-svn: 165608
* Pass into the AttributeWithIndex::get method an ArrayRef of attributeBill Wendling2012-10-104-84/+95
| | | | | | enums. These are then created via the correct Attributes creation method. llvm-svn: 165607
* misched: fall-back to a target hook for instr bundles.Andrew Trick2012-10-101-3/+4
| | | | llvm-svn: 165606
* TODO commentAndrew Trick2012-10-101-0/+3
| | | | llvm-svn: 165605
* TableGen subtarget emitter cleanup.Andrew Trick2012-10-102-29/+39
| | | | | | Consistently evaluate Aliases and Sequences recursively. llvm-svn: 165604
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-1012-115/+126
| | | | | | | | Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. llvm-svn: 165603
* misched: Generate IsBuffered flag for machine resources.Andrew Trick2012-10-102-6/+13
| | | | llvm-svn: 165602
* whitespaceAndrew Trick2012-10-101-3/+3
| | | | llvm-svn: 165601
* Place temporary LTO files into their own subdirectory.Bill Wendling2012-10-103-5/+5
| | | | llvm-svn: 165599
* Have 'addFnAttr' take the attribute enum value. Then have it build the ↵Bill Wendling2012-10-104-28/+19
| | | | | | attribute object and add it appropriately. No functionality change. llvm-svn: 165595
* Test case for r165480.Craig Topper2012-10-101-0/+10
| | | | llvm-svn: 165594
* Reorder some parts of the td file to by in alphabetical orderReed Kotler2012-10-101-64/+75
| | | | llvm-svn: 165590
* Adding comments to clarify the reason for non-standard style in these files.Andrew Kaylor2012-10-104-8/+30
| | | | | | Patch committed on behalf of Kirill Uhanov llvm-svn: 165589
* Cosmetic changesAndrew Kaylor2012-10-102-4/+4
| | | | llvm-svn: 165588
* This patch adds new functions to the SectionRef and ObjectFile interfaces to ↵Andrew Kaylor2012-10-106-1/+41
| | | | | | | | determine whether or not a section is meant to be read-only. These functions will be used by the MCJIT RuntimeDyld to give hints to the memory manager during the object loading process in a future patch. Patch by Ashok Thirumurthi. llvm-svn: 165586
* Implement MipsTargetLowering::CanLowerReturn.Akira Hatanaka2012-10-103-1/+266
| | | | | | Patch by Sasa Stankovic. llvm-svn: 165585
* Revert "Use a special path to place the .o files in."Bob Wilson2012-10-093-6/+3
| | | | | | This reverts commit 165428 in an attempt to get our buildbots going. llvm-svn: 165574
* Add extra vim swap file patternMichael Liao2012-10-091-0/+1
| | | | llvm-svn: 165569
* When expanding atomic load arith instructions, do not lose target flags. ↵Evan Cheng2012-10-092-44/+63
| | | | | | rdar://12453106 llvm-svn: 165568
* misched: Add computeInstrLatency to TargetSchedModel.Andrew Trick2012-10-092-0/+32
| | | | llvm-svn: 165566
* misched: Doxument the TargetSchedule API.Andrew Trick2012-10-091-7/+22
| | | | llvm-svn: 165565
* misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for ↵Andrew Trick2012-10-092-8/+14
| | | | | | external users of TargetSchedule. llvm-svn: 165564
* misched: Remove LoopDependencies heuristic.Andrew Trick2012-10-092-110/+1
| | | | | | This wasn't contributing anything significant to postRA heuristics except compile time (by my measurements) and will be replaced by a more general heuristic for cross-region dependencies within the scheduler itself. llvm-svn: 165563
* Use the attribute builder to add attributes to call/invoke instruction. No ↵Bill Wendling2012-10-092-40/+51
| | | | | | functionality change intended. llvm-svn: 165562
* Initial assembler implementation of Mips load address macroJack Carter2012-10-093-6/+122
| | | | | | | | | | | | | | | | | | | | | | | | This patch provides initial implementation of load address macro instruction for Mips. We have implemented two kinds of expansions with their variations depending on the size of immediate operand: 1) load address with immediate value directly: * la d,j => addiu d,$zero,j (for -32768 <= j <= 65535) * la d,j => lui d,hi16(j) ori d,d,lo16(j) (for any other 32 bit value of j) 2) load load address with register offset value * la d,j(s) => addiu d,s,j (for -32768 <= j <= 65535) * la d,j(s) => lui d,hi16(j) (for any other 32 bit value of j) ori d,d,lo16(j) addu d,d,s This patch does not cover the case when the address is loaded from the value of the label or function. Contributer: Vladimir Medic llvm-svn: 165561
* Add count() method to MapVectorDouglas Gregor2012-10-091-0/+5
| | | | llvm-svn: 165559
* Add in some interfaces that will allow easier access to the pointer address ↵Micah Villmow2012-10-093-3/+25
| | | | | | space. llvm-svn: 165554
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