misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for external users of TargetSchedule.

llvm-svn: 165564

2 files changed, 14 insertions, 8 deletions

diff --git a/llvm/include/llvm/CodeGen/TargetSchedule.h b/llvm/include/llvm/CodeGen/TargetSchedule.h
index 541ee66c0cc..ffcb793fc6b 100644
--- a/llvm/include/llvm/CodeGen/TargetSchedule.h
+++ b/llvm/include/llvm/CodeGen/TargetSchedule.h
@@ -45,11 +45,11 @@ public:
   /// Return true if this machine model includes an instruction-level scheduling
   /// model. This is more detailed than the course grain IssueWidth and default
   /// latency properties, but separate from the per-cycle itinerary data.
-  bool hasInstrSchedModel() const { return SchedModel.hasInstrSchedModel(); }
+  bool hasInstrSchedModel() const;
 
   /// Return true if this machine model includes cycle-to-cycle itinerary
   /// data. This models scheduling at each stage in the processor pipeline.
-  bool hasInstrItineraries() const { return !InstrItins.isEmpty(); }
+  bool hasInstrItineraries() const;
 
   /// computeOperandLatency - Compute and return the latency of the given data
   /// dependent def and use when the operand indices are already known. UseMI
diff --git a/llvm/lib/CodeGen/TargetSchedule.cpp b/llvm/lib/CodeGen/TargetSchedule.cpp
index 2c98982ee25..6e7cccce421 100644
--- a/llvm/lib/CodeGen/TargetSchedule.cpp
+++ b/llvm/lib/CodeGen/TargetSchedule.cpp
@@ -27,6 +27,14 @@ static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
 static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
   cl::desc("Use InstrItineraryData for latency lookup"));
 
+bool TargetSchedModel::hasInstrSchedModel() const {
+  return EnableSchedModel && SchedModel.hasInstrSchedModel();
+}
+
+bool TargetSchedModel::hasInstrItineraries() const {
+  return EnableSchedItins && !InstrItins.isEmpty();
+}
+
 void TargetSchedModel::init(const MCSchedModel &sm,
                             const TargetSubtargetInfo *sti,
                             const TargetInstrInfo *tii) {
@@ -47,14 +55,12 @@ int TargetSchedModel::getDefLatency(const MachineInstr *DefMI,
   if (FindMin) {
     // If MinLatency is invalid, then use the itinerary for MinLatency. If no
     // itinerary exists either, then use single cycle latency.
-    if (SchedModel.MinLatency < 0
-        && !(EnableSchedItins && hasInstrItineraries())) {
+    if (SchedModel.MinLatency < 0 && !hasInstrItineraries()) {
       return 1;
     }
     return SchedModel.MinLatency;
   }
-  else if (!(EnableSchedModel && hasInstrSchedModel())
-           && !(EnableSchedItins && hasInstrItineraries())) {
+  else if (!hasInstrSchedModel() && !hasInstrItineraries()) {
     return TII->defaultDefLatency(&SchedModel, DefMI);
   }
   // ...operand lookup required
@@ -123,7 +129,7 @@ unsigned TargetSchedModel::computeOperandLatency(
   if (DefLatency >= 0)
     return DefLatency;
 
-  if (EnableSchedItins && hasInstrItineraries()) {
+  if (hasInstrItineraries()) {
     int OperLatency = 0;
     if (UseMI) {
       OperLatency =
@@ -145,7 +151,7 @@ unsigned TargetSchedModel::computeOperandLatency(
                               TII->defaultDefLatency(&SchedModel, DefMI));
     return InstrLatency;
   }
-  assert(!FindMin && EnableSchedModel && hasInstrSchedModel() &&
+  assert(!FindMin && hasInstrSchedModel() &&
          "Expected a SchedModel for this cpu");
   const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
   unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);