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* [Hexagon] Adding zxtb instruction.Colin LeMahieu2014-11-243-5/+53
| | | | llvm-svn: 222660
* InstCombine: Don't create an unused instructionDavid Majnemer2014-11-242-2/+11
| | | | | | | | | | We would create an instruction but not inserting it. Not inserting the unused instruction would lead us to verification failure. This fixes PR21653. llvm-svn: 222659
* [mips][microMIPS] Fix JRADDIUSP instructionJozef Kolek2014-11-242-5/+2
| | | | | | | | | Fix JRADDIUSP instruction, remove delay slot flag because this instruction doesn't have delay slot. Differential Revision: http://reviews.llvm.org/D6365 llvm-svn: 222658
* Added comment about llvm_execute_on_thread waiting for thread to complete.Yaron Keren2014-11-241-1/+2
| | | | llvm-svn: 222654
* [mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructionsJozef Kolek2014-11-247-0/+209
| | | | | | Differential Revision: http://reviews.llvm.org/D5122 llvm-svn: 222653
* [mips][microMIPS] Implement 16-bit instructions registers including ZERO ↵Jozef Kolek2014-11-243-0/+41
| | | | | | | | | | instead of S0 Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17. Differential Revision: http://reviews.llvm.org/D5780 llvm-svn: 222652
* [Mips] Update MIPS relocations listSimon Atanasyan2014-11-241-0/+28
| | | | | | No functional changes. llvm-svn: 222651
* Replace a comment that says 'unreachable' with llvm_unreachable in TableGen ↵Craig Topper2014-11-241-1/+1
| | | | | | AsmWriter output. llvm-svn: 222650
* Removing a variable that is initialized but never read. The original author ↵Aaron Ballman2014-11-241-6/+2
| | | | | | has been alerted to the warning, in case this variable is meant to be used. Fixes -Werror builds in the meantime. llvm-svn: 222649
* [mips][microMIPS] Implement disassembler support for 16-bit instructionsJozef Kolek2014-11-244-14/+147
| | | | | | | | | | | With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
* [X86] Improved target specific combine on VSELECT dag nodes.Andrea Di Biagio2014-11-243-153/+192
| | | | | | | | | | | This patch teaches function 'transformVSELECTtoBlendVECTOR_SHUFFLE' how to convert VSELECT dag nodes to shuffles on targets that do not have SSE4.1. On pre-SSE4.1 targets, we can still perform blend operations using movss/movsd. Also, removed a target specific combine that performed a premature lowering of VSELECT nodes to target specific MOVSS/MOVSD nodes. llvm-svn: 222647
* InstCombine: Don't assume DataLayout is always availableDavid Majnemer2014-11-242-1/+22
| | | | | | | | | We tried to get the result of DataLayout::getLargestLegalIntTypeSize but we didn't have a DataLayout. This resulted in opt crashing. This fixes PR21651. llvm-svn: 222645
* Support: Add *cast_or_null<> for pointer wrappersDuncan P. N. Exon Smith2014-11-242-0/+130
| | | | | | | | | | | | | | | | | | | | Fill in omission of `cast_or_null<>` and `dyn_cast_or_null<>` for types that wrap pointers (e.g., smart pointers). Type traits need to be slightly stricter than for `cast<>` and `dyn_cast<>` to resolve ambiguities with simple types. There didn't seem to be any unit tests for pointer wrappers, so I tested `isa<>`, `cast<>`, and `dyn_cast<>` while I was in there. This only supports pointer wrappers with a conversion to `bool` to check for null. If in the future it's useful to support wrappers without such a conversion, it should be a straightforward incremental step to use the `simplify_type` machinery for the null check. In that case, the unit tests should be updated to remove the `operator bool()` from the `pointer_wrappers::PTy`. llvm-svn: 222644
* Detect best type for some static index tables instead of just using uint32_t ↵Craig Topper2014-11-241-15/+24
| | | | | | to reduce total data size. llvm-svn: 222643
* Converted back to Unix format (after my last commit 222632)Elena Demikhovsky2014-11-231-3241/+3241
| | | | llvm-svn: 222636
* [X86] Fixes bug in build_vector v4x32 loweringMichael Kuperstein2014-11-232-3/+23
| | | | | | | | | | | | | r222375 made some improvements to build_vector lowering of v4x32 and v4xf32 into an insertps, but it missed a case where: 1. A single extracted element is used twice. 2. The lower of the two non-zero indexes should be preserved, and the higher should be used for the dest mask. This caused a crash, since the source value for the insertps ends-up uninitialized. Differential Revision: http://reviews.llvm.org/D6377 llvm-svn: 222635
* Add missing override keywords.Craig Topper2014-11-231-2/+2
| | | | llvm-svn: 222634
* Tablegen output formatting fixes.Craig Topper2014-11-231-2/+4
| | | | llvm-svn: 222633
* Masked Vector Load and Store Intrinsics.Elena Demikhovsky2014-11-2332-3154/+4418
| | | | | | | | | | | | | | Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores. Added SDNodes for masked operations and lowering patterns for X86 code generator. Examples: <16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask) declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask) Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch. http://reviews.llvm.org/D6191 llvm-svn: 222632
* R600: Fix extloads of i1 on R600/EvergreenMatt Arsenault2014-11-232-13/+33
| | | | llvm-svn: 222631
* R600: Fix assert on copy of an i1 on pre-SIMatt Arsenault2014-11-231-1/+2
| | | | | | | i1 is not a legal type on Evergreen, so this combine proceeded and tried to produce a bitcast between i1 and i8. llvm-svn: 222630
* R600/SI: Add additional tests for i1 loadsMatt Arsenault2014-11-231-1/+22
| | | | llvm-svn: 222629
* R600/SI: Fix broken check lines and modernize prefixesMatt Arsenault2014-11-232-48/+50
| | | | | | Use -LABEL and remove -CHECK llvm-svn: 222628
* R600/SI: Fix missing -verify-machineinstrs on a testMatt Arsenault2014-11-231-1/+1
| | | | llvm-svn: 222627
* InstCombine: Propagate exact for (sdiv X, Pow2) -> (udiv X, Pow2)David Majnemer2014-11-222-2/+15
| | | | llvm-svn: 222625
* InstCombine: Propagate exact for (sdiv X, Y) -> (udiv X, Y)David Majnemer2014-11-222-1/+13
| | | | llvm-svn: 222624
* InstCombine: Propagate exact for (sdiv -X, C) -> (sdiv X, -C)David Majnemer2014-11-222-4/+15
| | | | llvm-svn: 222623
* Tidied up target triple OS detection. NFCSimon Pilgrim2014-11-226-14/+25
| | | | | | Use Triple::isOS*() helper functions where possible. llvm-svn: 222622
* Reduce size of some tables in tablegen register info output.Craig Topper2014-11-222-50/+54
| | | | | | Primarily done by using SequenceToOffsetTable to reduce the register pressure set tables and then sizing the indices into the tables appropriately. Size a few other table entries based on content as well. Reduces X86RegisterInfo.o by ~9k. llvm-svn: 222621
* InstCombine: Propagate exact in (udiv (lshr X,C1),C2) -> (udiv x,C1<<C2)David Majnemer2014-11-222-2/+16
| | | | llvm-svn: 222620
* [x86] Teach the vector shuffle yet another step of canonicalization.Chandler Carruth2014-11-221-2/+13
| | | | | | | | No functionality changed yet, but this will prevent subsequent patches from having to handle permutations of various interleaved shuffle patterns. llvm-svn: 222614
* InstCombine: Propagate NSW/NUW for X*(1<<Y) -> X<<YDavid Majnemer2014-11-222-4/+33
| | | | llvm-svn: 222613
* InstCombine: Propagate NSW for -X * -Y -> X * YDavid Majnemer2014-11-222-3/+19
| | | | llvm-svn: 222612
* InstSimplify: Simplify (sub 0, X) -> X if it's NUWDavid Majnemer2014-11-222-11/+10
| | | | | | This is a generalization of the X - (0 - Y) -> X transform. llvm-svn: 222611
* InstCombine: Silence a parenthesis warningDavid Majnemer2014-11-221-1/+1
| | | | llvm-svn: 222609
* [x86] Add some tests for a common unpack pattern of vector shuffle thatChandler Carruth2014-11-223-0/+72
| | | | | | | | | | has a remarkably unique and efficient lowering. While we get this some of the time already, we miss a few cases and there wasn't a principled reason we got it. We should at least test this. v8 already has tests for this pattern. llvm-svn: 222607
* InstCombine: Preserve nsw when folding X*(2^C) -> X << CDavid Majnemer2014-11-223-5/+7
| | | | llvm-svn: 222606
* InstCombine: Preserve nsw/nuw for ((X << C2)*C1) -> (X * (C1 << C2))David Majnemer2014-11-222-3/+28
| | | | llvm-svn: 222605
* InstCombine: Preserve nsw for (mul %V, -1) -> (sub 0, %V)David Majnemer2014-11-222-2/+14
| | | | llvm-svn: 222604
* [InstCombine] Re-commit of r218721 (Optimize icmp-select-icmp sequence)Gerolf Hoflehner2014-11-219-11/+428
| | | | | | | Fixes the self-host fail. Note that this commit activates dominator analysis in the combiner by default (like the original commit did). llvm-svn: 222590
* Fix transformation of add with pc argument to adr for non-immediateJoerg Sonnenberger2014-11-212-7/+33
| | | | | | arguments. llvm-svn: 222587
* [asan] remove old experimental codeKostya Serebryany2014-11-212-61/+0
| | | | llvm-svn: 222586
* R600/SI: Add a failing test case for offset order in ds_read2 instructionsTom Stellard2014-11-211-0/+44
| | | | llvm-svn: 222585
* R600/SI: Add an s_mov_b32 to patterns which use the M0RegClassTom Stellard2014-11-212-24/+8
| | | | | | | We need to use a s_mov_b32 rather than a copy, so that CSE will eliminate redundant moves to the m0 register. llvm-svn: 222584
* R600/SI: Emit s_mov_b32 m0, -1 before every DS instructionTom Stellard2014-11-217-41/+30
| | | | | | | | | | | | This s_mov_b32 will write to a virtual register from the M0Reg class and all the ds instructions now take an extra M0Reg explicit argument. This change is necessary to prevent issues with the scheduler mixing together instructions that expect different values in the m0 registers. llvm-svn: 222583
* R600/SI: Add SIFoldOperands passTom Stellard2014-11-217-28/+266
| | | | | | | This pass attempts to fold the source operands of mov and copy instructions into their uses. llvm-svn: 222581
* [mips][microMIPS] This patch implements functionality in MIPS delay slotJozef Kolek2014-11-215-12/+73
| | | | | | | | | | | filler such as if delay slot filler have to put NOP instruction into the delay slot of microMIPS BEQ or BNE instruction which uses the register $0, then instead of emitting NOP this instruction is replaced by the corresponding microMIPS compact branch instruction, i.e. BEQZC or BNEZC. Differential Revision: http://reviews.llvm.org/D3566 llvm-svn: 222580
* R600/SI: Mark s_mov_b32 and s_mov_b64 as rematerializableTom Stellard2014-11-211-0/+2
| | | | llvm-svn: 222579
* R600/SI: Use hex notation for constant in testTom Stellard2014-11-211-1/+1
| | | | llvm-svn: 222578
* [Hexagon] Adding sxth instruction.Colin LeMahieu2014-11-214-8/+20
| | | | llvm-svn: 222577
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