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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-11-23 02:57:52 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-11-23 02:57:52 +0000 |
| commit | 28638f1e2cd6f5b8fdd661e124c2808bafc92efa (patch) | |
| tree | 43fdf1b49215d409cca58e234d3dfb2e79dd06b4 /llvm | |
| parent | b7ebdffe3c8361baeddf6d44ce44a0a4a240b795 (diff) | |
| download | bcm5719-llvm-28638f1e2cd6f5b8fdd661e124c2808bafc92efa.tar.gz bcm5719-llvm-28638f1e2cd6f5b8fdd661e124c2808bafc92efa.zip | |
R600: Fix assert on copy of an i1 on pre-SI
i1 is not a legal type on Evergreen, so this combine proceeded
and tried to produce a bitcast between i1 and i8.
llvm-svn: 222630
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp index 2f95b74fcf7..9ff41afe30b 100644 --- a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp @@ -2155,7 +2155,8 @@ SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N, SDValue Value = SN->getValue(); EVT VT = Value.getValueType(); - if (isTypeLegal(VT) || SN->isVolatile() || !ISD::isNormalLoad(Value.getNode())) + if (isTypeLegal(VT) || SN->isVolatile() || + !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8) return SDValue(); LoadSDNode *LoadVal = cast<LoadSDNode>(Value); |
