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* Transforms: Use getFirstNonPHI to set the insertion point for PHIsJustin Bogner2013-09-273-2/+33
| | | | | | | | | | We were previously using getFirstInsertionPt to insert PHI instructions when vectorizing, but getFirstInsertionPt also skips past landingpads, causing this to generate invalid IR. We can avoid this issue by using getFirstNonPHI instead. llvm-svn: 191526
* [SystemZ] Rein back the use of block operationsRichard Sandiford2013-09-275-143/+101
| | | | | | | | | | | | | | The backend tries to use block operations like MVC, NC, OC and XC for simple scalar operations. For correctness reasons, it rejects any case in which the regions might partially overlap. However, for performance reasons, it should also reject cases where the regions might be equal, since the instruction might then not use the fast path. This fixes a performance regression seen in bzip2. We may want to limit the optimisation even more in future, or even remove it entirely, but I'll try with this for now. llvm-svn: 191525
* [SystemZ] Improve handling of PC-relative addressesRichard Sandiford2013-09-276-59/+127
| | | | | | | | | | | | | | The backend previously folded offsets into PC-relative addresses whereever possible. That's the right thing to do when the address can be used directly in a PC-relative memory reference (using things like LRL). But if we have a register-based memory reference and need to load the PC-relative address separately, it's better to use an anchor point that could be shared with other accesses to the same area of the variable. Fixes a FIXME. llvm-svn: 191524
* [mips][msa] Implemented insert.d intrinsic.Daniel Sanders2013-09-273-42/+66
| | | | | | | This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is further lowered into a sequence of insert.w's on MIPS32. llvm-svn: 191521
* ARM: Teach assembler to enforce constraints for ARM LDRD destination ↵Tilmann Scheller2013-09-273-21/+50
| | | | | | | | | | | | | | | | | | | register operands. As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints: LDRD<c> <Rt>, <Rt2>, ... (a) Rt must be even-numbered and not r14 (b) Rt2 must be R(t+1) If those two constraints are not met the result of executing the instruction will be unpredictable. Constraint (b) was already enforced, this commit adds support for constraint (a). Fixes rdar://14479793. llvm-svn: 191520
* [mips][msa] Implemented fill.d intrinsic.Daniel Sanders2013-09-273-12/+40
| | | | | | | This intrinsic is lowered into an equivalent BUILD_VECTOR which is further lowered into a sequence of insert.w's on MIPS32. llvm-svn: 191519
* [mips][msa] Implemented copy_[us].d intrinsic.Daniel Sanders2013-09-274-0/+67
| | | | | | | This intrinsic is lowered into equivalent copy_s.w instructions during legalization. llvm-svn: 191518
* [mips][msa] Rename arguments to MSA_INSERT_DESC_BASE to better match their ↵Daniel Sanders2013-09-271-6/+6
| | | | | | | | expected values. No functional change. llvm-svn: 191517
* [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.Daniel Sanders2013-09-274-0/+119
| | | | | | | For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. llvm-svn: 191515
* [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64Daniel Sanders2013-09-275-4/+325
| | | | | | | For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. llvm-svn: 191514
* Remove superfluous comment accidentally checked-in.Andrea Di Biagio2013-09-271-2/+0
| | | | llvm-svn: 191513
* [mips][msa] Added support for MSA registers to copyPhysRegDaniel Sanders2013-09-272-0/+140
| | | | llvm-svn: 191512
* [mips][msa] Added support for matching splati from normal IR (i.e. not ↵Daniel Sanders2013-09-2710-20/+157
| | | | | | | | intrinsics) Updated some of the vshf since they (correctly) emit splati's now llvm-svn: 191511
* Re-apply the change from r191393 with fix for pr17380.Andrea Di Biagio2013-09-272-0/+223
| | | | | | | | | | This change fixes the problem reported in pr17380 and re-add the dagcombine transformation ensuring that the value types are always legal if the transformation is triggered after Legalization took place. Added the test case from pr17380. llvm-svn: 191509
* [mips][msa] Added MSA.txt to describe instruction selection quirks.Daniel Sanders2013-09-271-0/+30
| | | | | | | | This file contains notes about the instruction selection for MSA. For example, it notes that ilvl.d is cannot be selected because ilvev.d covers the same cases and is selected instead of ilvl.d. llvm-svn: 191507
* Fix comment.Tilmann Scheller2013-09-271-1/+1
| | | | llvm-svn: 191505
* ARM: Teach assembler to enforce constraint for Thumb2 LDRD ↵Tilmann Scheller2013-09-272-0/+20
| | | | | | | | | | | | | | | | | (literal/immediate) destination register operands. LDRD<c> <Rt>, <Rt2>, <label> LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}] LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm> LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]! As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2. If this constraint is not met the result of executing the instruction will be unpredictable. Fixes rdar://14479780. llvm-svn: 191504
* [mips][msa] Tidy upDaniel Sanders2013-09-271-131/+119
| | | | | | | | | | | | lowerMSABinaryIntr, lowerMSABinaryImmIntr, lowerMSABranchIntr, and lowerMSAUnaryIntr were trivially small functions. Inlined them into their callers. lowerMSASplat now takes its callers SDLoc instead of making a new one. No functional change. llvm-svn: 191503
* [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal ↵Daniel Sanders2013-09-2757-58/+68
| | | | | | error when using it in FR=0 mode. llvm-svn: 191498
* [mips][msa] Expand all truncstores and loadexts for MSA as well as DSPDaniel Sanders2013-09-273-14/+48
| | | | llvm-svn: 191496
* [mips][msa] Added missing check in performSRACombineDaniel Sanders2013-09-272-0/+141
| | | | | | | | | | Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D1755 llvm-svn: 191495
* First check in. Modified a comment.Puyan Lotfi2013-09-271-1/+1
| | | | llvm-svn: 191491
* Put HasAVX512 predicate on some patterns to properly disable them when ↵Craig Topper2013-09-271-9/+11
| | | | | | AVX512 isn't enabled. Currently it works simply because the SSE and AVX version of the same patterns are checked first in the DAG isel table. llvm-svn: 191490
* Switch HasAVX to UseAVX in one spot to ensure that AVX512 form of VINSERTPS ↵Craig Topper2013-09-271-1/+1
| | | | | | is used in AVX512 mode. llvm-svn: 191489
* Removal some duplicate patterns.Craig Topper2013-09-271-8/+0
| | | | llvm-svn: 191488
* Fixing Intel format of the vshufpd instruction.Yunzhong Gao2013-09-273-2/+7
| | | | | | Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759 llvm-svn: 191481
* Revert "llvm-objdump: Dump COFF import table if -private-headers option is ↵Rui Ueyama2013-09-2715-390/+160
| | | | | | | | given." This reverts commit r191472 because it's failing on BE machine. llvm-svn: 191480
* Fix another -Wnon-pod-varargs error in r191472.Rui Ueyama2013-09-271-1/+1
| | | | llvm-svn: 191474
* Fix -Wnon-pod-varargs error in r191472.Rui Ueyama2013-09-271-6/+6
| | | | llvm-svn: 191473
* llvm-objdump: Dump COFF import table if -private-headers option is given.Rui Ueyama2013-09-2715-160/+390
| | | | | | | | | | | | | | | | This is a patch to add capability to llvm-objdump to dump COFF Import Table entries, so that we can write tests for LLD checking Import Table contents. llvm-objdump did not print anything but just file name if the format is COFF and -private-headers option is given. This is a patch adds capability for dumping DLL Import Table, which is specific to the COFF format. In this patch I defined a new iterator to iterate over import table entries. Also added a few functions to COFFObjectFile.cpp to access fields of the entry. Differential Revision: http://llvm-reviews.chandlerc.com/D1719 llvm-svn: 191472
* MCParser/Debug info: Accept line number 0 as a legitimate value, sinceAdrian Prantl2013-09-262-2/+3
| | | | | | | | CFE produces it to indicate artificial locations. c.f.: DWARF standard, Table 6.2: line -- An unsigned integer indicating a source line number. Lines are numbered beginning at 1. The compiler may emit the value 0 in cases where an instruction cannot be attributed to any source line. llvm-svn: 191471
* [mips][msa] Direct Object Emission for 3RF instructions.Jack Carter2013-09-263-112/+376
| | | | | | Patch by Matheus Almeida llvm-svn: 191461
* [mips][msa] Updates encoding of 3RF instructions to match the latest ↵Jack Carter2013-09-261-2/+2
| | | | | | | | | | revision of the MSA spec (1.06). This does not affect any of the existing output. Patch by Matheus Almeida llvm-svn: 191460
* Fix PR 17372: Emitting PLD for stack address for ARM Thumb2Weiming Zhao2013-09-262-0/+29
| | | | | | | t2PLDi12, t2PLDi8, t2PLDs was omitted in Thumb2InstrInfo. This patch fixes it. llvm-svn: 191441
* [PowerPC] Fix PR17354: Generate nop after local calls for PIC code.Bill Schmidt2013-09-262-1/+42
| | | | | | | | When generating code for shared libraries, even local calls may be intercepted, so we need a nop after the call for the linker to fix up the TOC. Test case adapted from the one provided in PR17354. llvm-svn: 191440
* Revert r191393 since it caused pr17380.Andrea Di Biagio2013-09-262-201/+0
| | | | llvm-svn: 191438
* [Sparc] Implements exception handling in SPARC with DwarfCFI.Venkatraman Govindaraju2013-09-265-4/+138
| | | | llvm-svn: 191432
* Implements parsing and emitting of .cfi_window_save in MC.Venkatraman Govindaraju2013-09-269-2/+112
| | | | llvm-svn: 191431
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-2612-372/+1896
| | | | | | Patch by Artyom Skrobov. llvm-svn: 191428
* PPC: Allow partial fills in writeNopData()David Majnemer2013-09-262-5/+11
| | | | | | | | | | | | | | | | | | When asked to pad an irregular number of bytes, we should fill with zeros. This is consistent with the behavior specified in the AIX Assembler Language Reference as well as other LLVM and binutils assemblers. N.B. There is a small deviation from binutils' PPC assembler: when handling pads which are greater than 4 bytes but not mod 4, binutils will not emit any NOP sequences at all and only use zeros. This may or may not be a bug but there is no excellent rationale as to why that behavior is important to emulate. If that behavior is needed, we can change writeNopData() to behave in the same way. This fixes PR17352. llvm-svn: 191426
* Add links to cross-compilation docs from getting startedRenato Golin2013-09-261-0/+4
| | | | llvm-svn: 191425
* Added temp flag -misched-bench for staging in default changes.Andrew Trick2013-09-265-4/+22
| | | | llvm-svn: 191423
* whitespaceAndrew Trick2013-09-261-2/+2
| | | | llvm-svn: 191422
* PPC: Do not introduce ISD nodes for fctid and fctiwDavid Majnemer2013-09-263-8/+6
| | | | llvm-svn: 191421
* PPC: Add support for fctid and fctiwDavid Majnemer2013-09-264-8/+20
| | | | | | | | | Encodings were checked against the Power ISA documents and double checked against binutils. This fixes PR17350. llvm-svn: 191419
* [mips][msa] Direct Object Emission for 3R instructions.Jack Carter2013-09-264-330/+1122
| | | | | | | | This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
* [mips][msa] Updates encoding of 3R instructions to match the latest revision ↵Jack Carter2013-09-261-9/+9
| | | | | | | | | | | of the MSA spec (1.06). Internal changes only. Patch by Matheus Almeida llvm-svn: 191414
* [mips][msa] Direct Object Emission for 2RF instructions.Jack Carter2013-09-252-41/+126
| | | | | | Patch by Matheus Almeida llvm-svn: 191413
* [mips][msa] Direct Object Emission support for the MSA instruction set. Jack Carter2013-09-256-8/+247
| | | | | | | | | | In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida llvm-svn: 191412
* [mips][msa] Updates encoding of 2RF instructions to match the latest ↵Jack Carter2013-09-251-4/+4
| | | | | | | | | | | | revision of the MSA spec (1.06). This only changes internal encodings and doesn't affect output. Patch by Matheus Almeida llvm-svn: 191411
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