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| author | Yunzhong Gao <Yunzhong_Gao@playstation.sony.com> | 2013-09-27 01:44:23 +0000 |
|---|---|---|
| committer | Yunzhong Gao <Yunzhong_Gao@playstation.sony.com> | 2013-09-27 01:44:23 +0000 |
| commit | 4467f33e3c397a6cf67258243fbddc53178c6ce8 (patch) | |
| tree | cf253ad0c1c8add247e7dbd2cd4e38b1d7f00877 /llvm | |
| parent | 333d28a0bb9387fbc55b791c1e652fb780cea4e4 (diff) | |
| download | bcm5719-llvm-4467f33e3c397a6cf67258243fbddc53178c6ce8.tar.gz bcm5719-llvm-4467f33e3c397a6cf67258243fbddc53178c6ce8.zip | |
Fixing Intel format of the vshufpd instruction.
Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759
llvm-svn: 191481
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/X86/intel-syntax.txt | 3 | ||||
| -rw-r--r-- | llvm/test/MC/X86/intel-syntax.s | 2 |
3 files changed, 7 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index be0f6c54dd5..8de13362f13 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -2553,10 +2553,10 @@ defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32, "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", memopv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L; defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64, - "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}", + "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V; defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64, - "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}", + "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L; let Constraints = "$src1 = $dst" in { diff --git a/llvm/test/MC/Disassembler/X86/intel-syntax.txt b/llvm/test/MC/Disassembler/X86/intel-syntax.txt index 6a63102eaa7..3689525d92f 100644 --- a/llvm/test/MC/Disassembler/X86/intel-syntax.txt +++ b/llvm/test/MC/Disassembler/X86/intel-syntax.txt @@ -105,6 +105,9 @@ # CHECK: retf 0x66 0xcb +# CHECK: vshufpd xmm0, xmm1, xmm2, 1 +0xc5 0xf1 0xc6 0xc2 0x01 + # CHECK: vpgatherqq ymm2, qword ptr [rdi + 2*ymm1], ymm0 0xc4 0xe2 0xfd 0x91 0x14 0x4f diff --git a/llvm/test/MC/X86/intel-syntax.s b/llvm/test/MC/X86/intel-syntax.s index f63513919ad..9677da731c1 100644 --- a/llvm/test/MC/X86/intel-syntax.s +++ b/llvm/test/MC/X86/intel-syntax.s @@ -69,6 +69,8 @@ _main: mov QWORD PTR FS:320, RAX // CHECK: movq %rax, %fs:20(%rbx) mov QWORD PTR FS:20[rbx], RAX +// CHECK: vshufpd $1, %xmm2, %xmm1, %xmm0 + vshufpd XMM0, XMM1, XMM2, 1 // CHECK: vpgatherdd %xmm8, (%r15,%xmm9,2), %xmm1 vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8 // CHECK: movsd -8, %xmm5 |
