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* Ignore NumberHack and give each SubRegIndex instance a unique enum value ↵Jakob Stoklund Olesen2010-05-253-6/+9
| | | | | | | | | | | instead. This passes lit tests, but I'll give it a go through the buildbots to smoke out any remaining places that depend on the old SubRegIndex numbering. Then I'll remove NumberHack entirely. llvm-svn: 104615
* Use enums instead of literals for SystemZ subregistersJakob Stoklund Olesen2010-05-251-11/+11
| | | | llvm-svn: 104612
* Use enums instead of literals for X86 subregisters.Jakob Stoklund Olesen2010-05-252-11/+10
| | | | | | | The cases in getMatchingSuperRegClass cannot be broken up until the enums have unique values. llvm-svn: 104611
* Add missing implementation to the materialization of VFP misc. instructions ↵Zonr Chang2010-05-251-0/+43
| | | | | | (vmrs, vmsr and vmov (immediate)) llvm-svn: 104588
* Add support to MOVimm32 using movt/movw for ARM JITZonr Chang2010-05-253-2/+113
| | | | llvm-svn: 104587
* Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated.Bob Wilson2010-05-251-6/+6
| | | | | | | I don't know of any particular reason why that would be important, but neither can I see any reason to disallow it. llvm-svn: 104583
* Fix up instruction classes for Thumb2 RSB instructions to be consistent withBob Wilson2010-05-251-15/+15
| | | | | | | Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the condition codes, and allow RSBS instructions to be predicated. llvm-svn: 104582
* Clean up indentation.Bob Wilson2010-05-251-2/+2
| | | | llvm-svn: 104580
* Disable invalid coalescer assertion.Jakob Stoklund Olesen2010-05-251-1/+4
| | | | llvm-svn: 104574
* Use enums instead of literals in the ARM backend.Jakob Stoklund Olesen2010-05-252-18/+18
| | | | llvm-svn: 104573
* Print out the name of the function during SSC.Bill Wendling2010-05-241-1/+5
| | | | llvm-svn: 104572
* Switch SubRegSet to using symbolic SubRegIndicesJakob Stoklund Olesen2010-05-249-189/+197
| | | | llvm-svn: 104571
* Allow Thumb2 MVN instructions to set condition codes. The immediate operandBob Wilson2010-05-241-5/+5
| | | | | | version of t2MVN already allowed that, but not the register versions. llvm-svn: 104570
* diaggroup categories should take precedence over diag-specific groups.Chris Lattner2010-05-241-8/+9
| | | | llvm-svn: 104567
* Lose the dummiesJakob Stoklund Olesen2010-05-241-22/+0
| | | | llvm-svn: 104564
* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-2413-163/+207
| | | | | | | | | | | structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. llvm-svn: 104563
* Avoid adding duplicate function live-in's.Evan Cheng2010-05-243-2/+21
| | | | llvm-svn: 104560
* Fix an mmx movd encoding.Dan Gohman2010-05-242-4/+36
| | | | llvm-svn: 104552
* MC/X86: Add aliases for CMOVcc variants.Kevin Enderby2010-05-242-0/+143
| | | | llvm-svn: 104549
* Clean up some extra whitespace.Bob Wilson2010-05-241-12/+12
| | | | llvm-svn: 104544
* Thumb2 RSBS instructions were being printed without the 'S' suffix.Bob Wilson2010-05-242-6/+13
| | | | | | | Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR output and 'S' suffix in the same way as T2I_bin_s_irs. llvm-svn: 104531
* Do not emit line number entries for unknown debug values.Devang Patel2010-05-241-0/+3
| | | | | | This fixes recent regression in store.exp from gdb testsuite. llvm-svn: 104524
* LR is in GPR, not tGPR even in Thumb1 mode.Evan Cheng2010-05-242-4/+3
| | | | llvm-svn: 104518
* Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices areJakob Stoklund Olesen2010-05-241-0/+7
| | | | | | never used. llvm-svn: 104517
* Use SubRegIndex in SystemZ.Jakob Stoklund Olesen2010-05-243-17/+10
| | | | | | Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug. llvm-svn: 104515
* SubRegIndex'ize MipsJakob Stoklund Olesen2010-05-243-17/+10
| | | | llvm-svn: 104514
* SubRegIndex'ize MSP430Jakob Stoklund Olesen2010-05-241-1/+4
| | | | llvm-svn: 104513
* Fix a few places that depended on the numeric value of subreg indices.Jakob Stoklund Olesen2010-05-243-8/+19
| | | | | | Add assertions in places that depend on consecutive indices. llvm-svn: 104510
* Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enumsJakob Stoklund Olesen2010-05-2410-199/+186
| | | | | | from ARMRegisterInfo.h llvm-svn: 104508
* Rename X86 subregister indices to something shorter.Jakob Stoklund Olesen2010-05-248-106/+96
| | | | | | Use the tablegen-produced enums. llvm-svn: 104493
* Add the SubRegIndex TableGen class.Jakob Stoklund Olesen2010-05-2411-57/+94
| | | | | | | This is the beginning of purely symbolic subregister indices, but we need a bit of jiggling before the explicit numeric indices can be completely removed. llvm-svn: 104492
* Encode the Caml frametable by following what the comment says: the number of ↵Nicolas Geoffray2010-05-241-5/+22
| | | | | | | | descriptors is first emitted, and StackOffsets are emitted in 16 bits. llvm-svn: 104488
* Apply timeouts and memory limits in more places. In particular, whenDuncan Sands2010-05-243-21/+40
| | | | | | | | bugpoint does "Running the code generator to test for a crash" this gets you a crash if llc goes into an infinite loop or uses up vast amounts of memory. llvm-svn: 104485
* llvm-mc: Use EmitIntValue where possible, which makes the API calls from the ↵Daniel Dunbar2010-05-231-3/+6
| | | | | | AsmParser and CodeGen line up better. llvm-svn: 104467
* llvm-mc: Use AddBlankLine in asm parser. This makes transliteration match ↵Daniel Dunbar2010-05-231-0/+9
| | | | | | the input much more closely, and also makes the API calls from the AsmParser and CodeGen line up better. llvm-svn: 104466
* MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches.Daniel Dunbar2010-05-235-2/+229
| | | | llvm-svn: 104463
* VDUP doesn't support vectors with 64-bit elements.Bob Wilson2010-05-231-2/+2
| | | | llvm-svn: 104455
* MC/X86: Subdivide immediates a bit more, so that we properly recognize ↵Daniel Dunbar2010-05-224-38/+195
| | | | | | | | | | | immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
* tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses ↵Daniel Dunbar2010-05-223-15/+19
| | | | | | instead of just one. llvm-svn: 104452
* MC/X86: Add alias for setz, setnz, jz, jnz.Daniel Dunbar2010-05-222-1/+22
| | | | llvm-svn: 104435
* Trivial change to dump() function for SparseBitVectorJohn Mosby2010-05-221-6/+10
| | | | llvm-svn: 104433
* Implement @llvm.returnaddress. rdar://8015977.Evan Cheng2010-05-2222-32/+185
| | | | llvm-svn: 104421
* Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.Jim Grosbach2010-05-228-3/+63
| | | | | | | Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match longjmp. llvm-svn: 104419
* This test is darwin only. Make it so(tm).Eric Christopher2010-05-221-1/+1
| | | | llvm-svn: 104418
* Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented byBob Wilson2010-05-224-31/+119
| | | | | | | | copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll tests, so I tweaked those tests to keep that code from being optimized away. Radar 7872877. llvm-svn: 104415
* Add full bss data support for darwin tls variables.Eric Christopher2010-05-223-3/+53
| | | | llvm-svn: 104414
* Collect variable information during endFunction() instead of beginFunction().Devang Patel2010-05-221-12/+12
| | | | llvm-svn: 104412
* Add a new section and accessor for TLS data.Eric Christopher2010-05-221-0/+7
| | | | llvm-svn: 104411
* Clean up extra whitespace.Bob Wilson2010-05-211-1/+0
| | | | llvm-svn: 104410
* Make this LookAheadLimit, not the uninitialized LookAheadLeft.Eric Christopher2010-05-211-1/+1
| | | | | | Evan please verify! llvm-svn: 104408
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