diff options
| author | Bob Wilson <bob.wilson@apple.com> | 2010-05-24 22:41:19 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-05-24 22:41:19 +0000 |
| commit | 91b2b8540cca424fd0fe3ca5e311ee14b7fba894 (patch) | |
| tree | f90239f0282b2306438df961f89d72dfe5f3e4af /llvm | |
| parent | fb58515bc3a1c521dc7ac71bf7304e8097501ec6 (diff) | |
| download | bcm5719-llvm-91b2b8540cca424fd0fe3ca5e311ee14b7fba894.tar.gz bcm5719-llvm-91b2b8540cca424fd0fe3ca5e311ee14b7fba894.zip | |
Allow Thumb2 MVN instructions to set condition codes. The immediate operand
version of t2MVN already allowed that, but not the register versions.
llvm-svn: 104570
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index c23ae5d967f..7e01312631c 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -185,8 +185,8 @@ multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode, let Inst{15} = 0; } // register - def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr, - opc, ".w\t$dst, $src", + def r : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr, + opc, ".w\t$dst, $src", [(set GPR:$dst, (opnode GPR:$src))]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; @@ -198,9 +198,9 @@ multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode, let Inst{5-4} = 0b00; // type } // shifted register - def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi, - opc, ".w\t$dst, $src", - [(set GPR:$dst, (opnode t2_so_reg:$src))]> { + def s : T2sI<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi, + opc, ".w\t$dst, $src", + [(set GPR:$dst, (opnode t2_so_reg:$src))]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-21} = opcod; |
