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* [X86][SSE] Regenerate multiple combine testsSimon Pilgrim2016-09-201-50/+55
| | | | llvm-svn: 281973
* move variables closer to their uses; add FIXMEs; NFCSanjay Patel2016-09-201-10/+10
| | | | llvm-svn: 281972
* [AMDGPU][mc] Add regression tests for Bug 28168Artem Tamazov2016-09-201-0/+10
| | | | llvm-svn: 281967
* AVX-512: Fixed a bug in lowering saturated operations on KNL.Elena Demikhovsky2016-09-202-2/+18
| | | | | | | | The generated code is still not optimal. Differential Revision: https://reviews.llvm.org/D24723 llvm-svn: 281966
* [AMDGPU] Refactor VOP3 instruction TD definitionsValery Pykhtin2016-09-206-373/+448
| | | | | | Differential revision: https://reviews.llvm.org/D24664 llvm-svn: 281965
* Make llvm::ConvertDebugDeclareToDebugValue() be a void function (NFC)Keith Walker2016-09-202-11/+8
| | | | | | | | | | The routines llvm::ConvertDebugDeclareToDebugValue() always returned a true value which was never checked at the call site; change the function return type to void. This NFC cleanup was approved in the review https://reviews.llvm.org/D23715 llvm-svn: 281964
* AMDGPU: Improve documentation.Nikolay Haustov2016-09-202-68/+218
| | | | | | | | | | | | | | | | | Summary: Add links to ISA manuals and ABI. Add text about assembler syntax. Add info about instructions operands. Add instruction examples for each encoding. Update directives section, add missing .amdgpu_hsa_kernel. Reviewers: tstellarAMD, SamWot, vpykhtin Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, artem.tamazov, llvm-commits Differential Revision: https://reviews.llvm.org/D24724 llvm-svn: 281962
* Reverting revision 281960 due to test failures.Dorit Nuzman2016-09-202-120/+2
| | | | llvm-svn: 281961
* [SROA] Preserve llvm.mem.parallel_loop_access metadata.Dorit Nuzman2016-09-202-2/+120
| | | | | | | | | | | | SROA doesn't preserve the llvm.mem.parallel_loop_access metadata when it transforms loads/stores. This patch fixes a couple occurences of this issue. (Partially addresses PR28981). Differential Revision: https://reviews.llvm.org/D23549 llvm-svn: 281960
* [AVX-512] Teach X86InstrInfo::copyPhysReg to use a 512-bit move if ↵Craig Topper2016-09-203-5/+38
| | | | | | | | XMM16-XMM31 or YMM16-YMM31 are the source or dest of the copy and VLX is not supported. This can happen with SUBREG_TO_REG of ZMM16-ZMM31. Fixes PR30430. llvm-svn: 281959
* [AVX-512] Use 512-bit vcvtps2ph/vcvtph2ps to implement fp_to_f16/f16_to_fp ↵Craig Topper2016-09-204-397/+796
| | | | | | | | when F16C and VLX are not supported. Fixes PR23941. llvm-svn: 281958
* BranchFolder: Fix invalid undef flags after merge.Matthias Braun2016-09-202-5/+43
| | | | | | | | | | It is legal to merge instructions with different undef flags; However we must drop the undef flag from the merged instruction if it isn't present everywhere. This fixes http://llvm.org/PR30199 llvm-svn: 281957
* Machine{Instr|Operand}: Clarify some isIdenticalTo() subtleties.Matthias Braun2016-09-202-4/+5
| | | | llvm-svn: 281956
* [RegisterBankInfo] Avoid heap allocation in InstructionMapping.Quentin Colombet2016-09-201-2/+3
| | | | | | | | | | | Use SmallVector instead of dynamically allocated arrays for the mapping of the operands in the InstructionMapping. That way we avoid heap allocation for most of the cases. Ultimately, we should not have to rely on such tricky, the instances of InstructionMapping would be TableGen'ed. This improves the compilation time of the RegBankSelect pass. llvm-svn: 281955
* [x86] fix variable names; NFCSanjay Patel2016-09-201-22/+23
| | | | llvm-svn: 281953
* [sanitizer-coverage] add comdat to coverage guards if neededKostya Serebryany2016-09-202-0/+15
| | | | llvm-svn: 281952
* [x86] auto-generate checksSanjay Patel2016-09-191-12/+18
| | | | llvm-svn: 281950
* [LCSSA] Cache LoopExits to avoid wasted workPhilip Reames2016-09-191-3/+9
| | | | | | | | | | When looking at the scribus_1.3 example from https://llvm.org/bugs/show_bug.cgi?id=10584, I noticed that we were spending a large amount of time computing loop exits in LCSSA. This code appears to be written with the assumption that LoopExits are stored in the Loop and thus cheap to query. This is not true, so we should cache the result across the potentially long running loop which tends to visit a small handful of Loops. On the particular example from 10584, this change drops the time spent in LCSSA computation by about 80%. Differential Revision: https://reviews.llvm.org/D24509 llvm-svn: 281949
* [RegisterBankInfo] Adapt call to std::fill due to use of SmallVector.Quentin Colombet2016-09-191-1/+1
| | | | | | This was meant to be commited with my previous commit. llvm-svn: 281948
* Merge branch 'ADCE5'David Callahan2016-09-191-2/+39
| | | | llvm-svn: 281947
* [Kaleidoscope] Make Chapter 2 use llvm::make_unique, rather than a helper.Lang Hames2016-09-192-22/+15
| | | | | | | This essentially reverts r251936, minimizing the difference between Chapter2 and Chapter 3, and making Chapter 2's code match the tutorial text. llvm-svn: 281945
* [x86] use getSignBit() to simplify code; NFCISanjay Patel2016-09-191-4/+3
| | | | llvm-svn: 281944
* Move the armv8.1-a ras test to a negative with noras test as ras isEric Christopher2016-09-192-5/+5
| | | | | | included in armv8.1-a by default and so we weren't testing anything. llvm-svn: 281941
* BitcodeWriter: fix emission of invoke when calling a var-arg function with ↵Mehdi Amini2016-09-192-1/+19
| | | | | | operand bundles llvm-svn: 281940
* Misleading comments of SplitBlockAndInsertIfThenElse in BasicBlockUtils.hEvgeniy Stepanov2016-09-191-2/+2
| | | | | | | | | | | The comments of SplitBlockAndInsertIfThenElse say the SplitBefore instruction will stay in the old block. But according to the implementation(split the block at SplitBefore by using splitBasicBlock), the SplitBefore will be moved to the new block. This patch fixes the comments. Patch by Zhe Yu Wu. llvm-svn: 281939
* [X86][SSE] Updated vector abs testsSimon Pilgrim2016-09-191-80/+167
| | | | | | Renamed and added v2i64 / v4i64 tests llvm-svn: 281937
* [libFuzzer] use sleep() instead of std::this_thread::sleep_for to avoid ↵Kostya Serebryany2016-09-191-1/+1
| | | | | | coverage from instrumented libc++ llvm-svn: 281933
* Handle early inline for hot callsites that reside in the same basic block.Dehao Chen2016-09-193-4/+9
| | | | | | | | | | | | Summary: Callsites in the same basic block should share the same hotness. This patch checks for the hottest callsite in the same basic block, and use the hotness for all callsites in that basic block for early inline decisions. It also fixes the test to add "-S" so theat the "CHECK-NOT" is actually checking the content. Reviewers: dnovillo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D24734 llvm-svn: 281927
* [RegisterBankInfo] Avoid heap allocation in most cases.Quentin Colombet2016-09-192-2/+3
| | | | | | | | | | | The OperandsMapper class is used heavy in RegBankSelect and each instantiation triggered a heap allocation for the array of operands. Instead, use a SmallVector with a big enough size such that most of the cases do not have to use dynamically allocated memory. This improves the compile time of the RegBankSelect pass. llvm-svn: 281916
* LiveRangeCalc: Fix reporting of invalid vreg usage in liveness calculationMatthias Braun2016-09-192-3/+34
| | | | | | | | | | | | | Machine programs need a definition of each vreg before reaching a use (the definition may come from an IMPLICIT_DEF instruction). This class of errors is not detected by the MachineVerifier because of efficiency concerns. LiveRangeCalc used to report these problems, make it do that again (followup to r279625). Also use report_fatal_error() instead of llvm_unreachable() as the error reporting is only present in asserts build anyway. llvm-svn: 281914
* Only set branch weight during sample pgo annotation when max_weight of the ↵Dehao Chen2016-09-192-19/+20
| | | | | | | | | | | | | | branch is non-zero. Otherwise use default static profile to set branch probability. Summary: It does not make sense to set equal weights for all unkown branches as we have static branch prediction available. Reviewers: dnovillo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D24732 llvm-svn: 281912
* Use call target count to derive the call instruction weightDehao Chen2016-09-193-4/+21
| | | | | | | | | | | | Summary: The call target count profile is directly derived from LBR branch->target data. This is more reliable than instruction frequency profiles that could be moved across basic block boundaries. This patches uses call target count profile to annotate call instructions. Reviewers: davidxl, dnovillo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D24410 llvm-svn: 281911
* [asan] Support dynamic shadow address instrumentationEtienne Bergeron2016-09-192-7/+81
| | | | | | | | | | | | | | | | | | | Summary: This patch is adding the support for a shadow memory with dynamically allocated address range. The compiler-rt needs to export a symbol containing the shadow memory range. This is required to support ASAN on windows 64-bits. Reviewers: kcc, rnk, vitalybuka Subscribers: kubabrecka, dberris, llvm-commits, chrisha Differential Revision: https://reviews.llvm.org/D23354 llvm-svn: 281908
* [Support] Add StringRef::withNullAsEmpty()Zachary Turner2016-09-191-0/+4
| | | | | | | | | | | When porting large bodies of code from using const char* to StringRef, it is helpful to be able to treat nullptr as an empty string, since that it is often what it is used to indicate in C-style code. Differential Revision: https://reviews.llvm.org/D24697 llvm-svn: 281906
* Revert r281841, it does not work on Windows (PR30443).Nico Weber2016-09-191-722/+0
| | | | llvm-svn: 281905
* [AMDGPU] Refactor VOPC instruction TD definitionsValery Pykhtin2016-09-196-648/+1118
| | | | | | Differential Revision: https://reviews.llvm.org/D24546 llvm-svn: 281903
* [AArch64] Fix encoding for lsl #12 in add/sub immediatesDiana Picus2016-09-194-12/+27
| | | | | | | | | | | Whenever an add/sub immediate needs a fixup, we set that immediate field to zero, which is correct, but we also set the shift bits to zero, which is not true for instructions that use lsl #12. This patch makes sure that if lsl #12 was used, it will appear in the encoding of the instruction. Differential Revision: https://reviews.llvm.org/D23930 llvm-svn: 281898
* [AMDGPU] Fix s_branch with -1 offsetSam Kolton2016-09-192-5/+9
| | | | | | | | | | | | | | | | | | | Summary: In case s_branch instruction target is itself backend should emit offset -1 but instead it emit 0. ''' label: s_branch label // should emit [0xff,0xff,0x82,0xbf] ''' Tom, Matt: why are we adjusting fixup values in applyFixup() method instead of processFixup()? processFixup() is calling adjustFixupValue() but does nothing with its result. Reviewers: vpykhtin, artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl Differential Revision: https://reviews.llvm.org/D24671 llvm-svn: 281896
* Add @llvm.dbg.value entries for the phi node created by -mem2regKeith Walker2016-09-194-0/+134
| | | | | | | | | | | | | | | | | | | | | | | When phi nodes are created in the -mem2reg phase, the @llvm.dbg.declare entries are converted to @llvm.dbg.value entries at the place where the store instructions existed. However no entry is created to describe the resulting value of the phi node. The effect of this is especially noticeable in for loops which have a constant for the intial value; the loop control variable's location would be described as the intial constant value in the loop body once the -mem2reg optimization phase was run. This change adds the creation of the @llvm.dbg.value entries to describe variables whose location is the result of a phi node created in -mem2reg. Also when the phi node is finally lowered to a machine instruction it is important that the lowered "load" instruction is placed before the associated DEBUG_VALUE entry describing the value loaded. Differential Revision: https://reviews.llvm.org/D23715 llvm-svn: 281895
* [Thumb] Set correct initial mapping symbol for big-endian thumbOliver Stannard2016-09-192-1/+11
| | | | | | | | | | The initial mapping symbol state is set from the triple, but we only checked for the little-endian thumb triple, so could end up with an ARM mapping symbol for big-endian thumb. Differential Revision: https://reviews.llvm.org/D24553 llvm-svn: 281894
* ARM: check alignment before transforming ldr -> ldm (or similar).Tim Northover2016-09-193-8/+41
| | | | | | | | | ldm and stm instructions always require 4-byte alignment on the pointer, but we weren't checking this before trying to reduce code-size by replacing a post-indexed load/store with them. Unfortunately, we were also dropping this incormation in DAG ISel too, but that's easy enough to fix. llvm-svn: 281893
* [X86 Codegen Test] Divided masked_memop into several files. NFC.Elena Demikhovsky2016-09-193-9370/+436
| | | | | | The masked_memop.ll became huge. I extracted AVX-512 specific tests into separate files. llvm-svn: 281892
* [SimplifyCFG] Update (AND) IR flags when CSE'ing instructionsJames Molloy2016-09-192-2/+60
| | | | | | | | We were updating metadata but not IR flags. Because we pick an arbitrary instruction to be the CSE candidate, it comes down to luck (50% or less chance) if this results in broken codegen or not, which is why PR30373 which is actually not the fault of the commit it was bisected down to. Fixes PR30373. llvm-svn: 281889
* [X86,AVX-512] Use INSERT_SUBREG instead of SUBREG_TO_REG when the input is ↵Craig Topper2016-09-198-130/+146
| | | | | | | | not the output of an instruction. SUBREG_TO_REG is supposed to indicate that the super register has been zeroed, but we can't prove that if we don't know where it came from. llvm-svn: 281885
* [AVX-512] Add support for lowering fp_to_f16 and f16_to_fp when VLX is ↵Craig Topper2016-09-194-1633/+891
| | | | | | | | supported regardless of whether F16C is also supported. Still need to add support for lowering using AVX512F when neither VLX or F16C is supported. llvm-svn: 281884
* [llvm-cov] Emit a link to some documentationVedant Kumar2016-09-191-0/+7
| | | | llvm-svn: 281883
* [llvm-cov] Delete the NonCodeLines field, it was always deadVedant Kumar2016-09-199-42/+26
| | | | llvm-svn: 281882
* [XRay] ARM 32-bit no-Thumb support in LLVMDean Michael Berris2016-09-1917-63/+328
| | | | | | | | | | | | This is a port of XRay to ARM 32-bit, without Thumb support yet. The XRay instrumentation support is moving up to AsmPrinter. This is one of 3 commits to different repositories of XRay ARM port. The other 2 are: https://reviews.llvm.org/D23932 (Clang test) https://reviews.llvm.org/D23933 (compiler-rt) Differential Revision: https://reviews.llvm.org/D23931 llvm-svn: 281878
* [llvm-cov] Teach the coverage exporter about instantiation coverageVedant Kumar2016-09-197-16/+32
| | | | | | | While we're at it, re-use the logic from CoverageReport to compute summaries. llvm-svn: 281877
* [llvm-cov] Make a helper method static for re-use (NFC)Vedant Kumar2016-09-193-8/+9
| | | | llvm-svn: 281876
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