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* [SeparateConstOffsetFromGEP] Fix a typo. NFC.Haicheng Wu2017-12-191-1/+1
| | | | | | do CSE for to => do CSE to llvm-svn: 321098
* [X86] Regenerate popcnt testsSimon Pilgrim2017-12-191-1/+1
| | | | llvm-svn: 321093
* [GlobalISel][Legalizer] Fix crash when trying to lower G_FNEG of fp128 types.Amara Emerson2017-12-192-0/+47
| | | | | | | | | This doesn't add legalizer support, just prevents crashing so that we can gracefully fall back to SDAG. Fixes PR35690. llvm-svn: 321091
* [DAG] Elide overlapping storeNirav Dave2017-12-192-24/+23
| | | | | | | | | | | | | | | | | Summary: Extend overlapping store elision to handle overwrites of stores by larger stores. Nontemporal tests have been modified to add memory dependencies to prevent store elision. Reviewers: craig.topper, rnk, t.p.northover Subscribers: javed.absar, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40969 llvm-svn: 321089
* [X86][AVX512] Attempt target shuffle combining to different types instead of ↵Simon Pilgrim2017-12-1914-1094/+695
| | | | | | | | | | early-out We try to prevent shuffle combining to value types that would stop the folding of masked operations, but by just returning early, we were failing to try different shuffle types. The TODOs are all still relevant here to improve codegen but we're lacking test examples. llvm-svn: 321085
* [CodeGen] Move printing MO_CFIIndex operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-195-121/+164
| | | | | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. Before this patch we printed "<call frame instruction>" in the debug output. llvm-svn: 321084
* [CFGVPrinter] Fix -dot-cfg-onlyFrancis Visoiu Mistrih2017-12-191-4/+4
| | | | | | The refactoring in r281640 made -dot-cfg-only ignore the "-only" part. llvm-svn: 321079
* [ThinLTO][C-API] Correct api commentsBen Dunbobbin2017-12-192-11/+12
| | | | | | | | | | | | Negative values never disabled the pruning - they simply set high values for the pruning interval. The behaviour now is that negative values set the maximum pruning interval (which appears to have been the intention from the start) see https://reviews.llvm.org/D41231. I have adjusted the comments to reflect this, removed any inaccurate statements, and corrected any typos I spotted in the English. Differential Revision: https://reviews.llvm.org/D41279 llvm-svn: 321078
* [Support][CachePruning] Disable cache pruning regression fixBen Dunbobbin2017-12-194-6/+32
| | | | | | | | | | borked by: rL284966 (see: https://reviews.llvm.org/D25730). Previously, Interval was unsigned (see: CachePruning.h), replacing the type with std::chrono::seconds (which is signed) causes a regression in behaviour because the c-api intends negative values to translate to large positive intervals to *effectively* disable the pruning (see comments on: setCachePruningInterval()). Differential Revision: https://reviews.llvm.org/D41231 llvm-svn: 321077
* [X86] Fix uninitialized variable sanitizer warning from rL321074Simon Pilgrim2017-12-191-0/+1
| | | | llvm-svn: 321076
* [InlineCost] Skip volatile loads when looking for repeated loadsHaicheng Wu2017-12-192-1/+20
| | | | | | This is a follow-up fix of r320814. A test case is also added. llvm-svn: 321075
* [X86][SSE] Add cpu feature for aggressive combining to variable shufflesSimon Pilgrim2017-12-1910-498/+1362
| | | | | | | | | | | | As mentioned in D38318 and D40865, modern Intel processors prefer to combine multiple shuffles to a variable shuffle mask (PSHUFB/VPERMPS etc.) instead of having multiple stage 'fixed' shuffles which put more pressure on Port 5 (at the expense of extra shuffle mask loads). This patch provides a FeatureFastVariableShuffle target flag for Haswell+ CPUs that prefers combining 2 or more fixed shuffles to a single variable shuffle (default is 3 shuffles). The long term aim is to drive more of this from schedule data (probably via the MC) but we're not close to being ready for that yet. Differential Revision: https://reviews.llvm.org/D41323 llvm-svn: 321074
* [ARM] Register the Thumb2SizeReducePass. NFCDavid Green2017-12-194-2/+91
| | | | | | Also adds a simple test case. llvm-svn: 321072
* [Support] Add WritableMemoryBuffer classPavel Labath2017-12-193-61/+190
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The motivation here is LLDB, where we need to fixup relocations in mmapped files before their contents can be read correctly. The MemoryBuffer class does exactly what we need, *except* that it maps the file in read-only mode. WritableMemoryBuffer reuses the existing machinery for opening and mmapping a file. The only difference is in the argument to the mapped_file_region constructor -- we create a private copy-on-write mapping, so that we can make changes to the mapped data, but the changes aren't carried over to the underlying file. This patch is based on an initial version by Zachary Turner. Reviewers: mehdi_amini, rnk, rafael, dblaikie, zturner Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40291 llvm-svn: 321071
* [X86][SSE] Use (V)PHMINPOSUW for vXi8 SMAX/SMIN/UMAX/UMIN horizontal ↵Simon Pilgrim2017-12-195-631/+427
| | | | | | | | | | | | reductions (PR32841) Extension to D39729 which performed this for vXi16, with the same bit flipping to handle SMAX/SMIN/UMAX cases, vXi8 UMIN horizontal reductions can be performed. This makes use of the fact that by performing a pair-wise i8 SHUFFLE/UMIN before PHMINPOSUW, we both get the UMIN of each pair but also zero-extend the upper bits ready for v8i16. Differential Revision: https://reviews.llvm.org/D41294 llvm-svn: 321070
* Fix: [YAML] Always double quote UTF-8 charactersFrancis Visoiu Mistrih2017-12-191-1/+1
| | | | llvm-svn: 321069
* [YAML] Always double quote UTF-8 charactersFrancis Visoiu Mistrih2017-12-191-3/+3
| | | | llvm-svn: 321068
* [mips] Handle the emission of microMIPSr6 sll instruction when used as a nop.Simon Dardis2017-12-192-1/+47
| | | | | | | This instruction is encoded as zero, so we have handle that case when checking for unimplemented opcodes when producing the encoding for an instruction. llvm-svn: 321066
* [dwarfdump] Lookup needs to be an unsigned long long parameter.Jonas Devlieghere2017-12-191-2/+1
| | | | | | | | | | | Before this patch, dwarfdump's lookup parameter only accepts unsigned. Given that for many current platforms the load address already exceeds unsigned (e.g. arm64 w/ 0x100000000), dwarfdump needs an unsigned long long parameter. Patch by: Dr. Michael 'Mickey' Lauer <mickey@vanille-media.de> llvm-svn: 321064
* [JumpThreading] Restrict PRE across instructions that don't pass control to ↵Max Kazantsev2017-12-192-0/+117
| | | | | | | | | | | | | | successors PRE in JumpThreading should not be able to hoist copy of non-speculable loads across instructions that don't always transfer execution to their successors, otherwise they may introduce an unsafe load which otherwise would not be executed. The same problem for GVN was fixed as rL316975. Differential Revision: https://reviews.llvm.org/D40347 llvm-svn: 321063
* [FuzzMutate] Don't crash when mutator is unable to find operationIgor Laevsky2017-12-192-7/+16
| | | | | | Differential Revision: https://reviews.llvm.org/D41009 llvm-svn: 321062
* Treat sret arguments as being dereferenceable in ↵Bjorn Steinbrink2017-12-192-3/+14
| | | | | | | | | | | | getPointerDereferenceableBytes() Reviewers: rnk, hfinkel, efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41355 llvm-svn: 321061
* [X86] Don't extend v16i8 non-uniform shifts to v16i32 if we have BWI. Use ↵Craig Topper2017-12-195-169/+373
| | | | | | | | v16i16 instead. BWI supports shifting by word amounts. Even if VLX isn't support we can still widen to v32i16 and extract the lower half. For SKX its preferrable to not use 512-bit vector if we can. llvm-svn: 321059
* [X86] Use a specific list of MVTs in combineShiftRightArithmetic instead of ↵Craig Topper2017-12-191-2/+2
| | | | | | | | iterating over every integer VT and checking their size. Previously, we were checking for MVTs with sizes betwen 8 and 64 which only includes i8, i16, i32, and i64 today. But I don't think we should assume that and should list the types that are legal for x86. I also don't think we need i64 since type legalization is guaranteed to split those up. llvm-svn: 321058
* [X86] Remove unnecessary check for integer VT from combineShiftRightArithmetic.Craig Topper2017-12-191-1/+1
| | | | | | I doubt there's any way to create a ashr for an FP type. llvm-svn: 321057
* [X86] Remove dead code for turning vector shifts by large amounts into a ↵Craig Topper2017-12-191-36/+0
| | | | | | | | zero vector. Pretty sure these are handled by a target independent DAG combine that turns them into undef these days. llvm-svn: 321056
* [X86] Use ZERO_EXTEND instead of ANY_EXTEND when extending the shift amount ↵Craig Topper2017-12-191-1/+1
| | | | | | | | | | for a non-uniform shift. My reading of the SDM says that all bits of the shift amount are used. If the value of the element is larger than the number of bits the result the shift result is zero. So I think we need to zero_extend here to avoid garbage in the upper bits. In reality we lower any_extend as zero_extend so in most cases it would be hard to hit this. llvm-svn: 321055
* Fix APFloat from string conversion for InfSerguei Katkov2017-12-194-4/+26
| | | | | | | | | | | | | | | | | | The method IEEEFloat::convertFromStringSpecials() does not recognize the "+Inf" and "-Inf" strings but these strings are printed for the double Infinities by the IEEEFloat::toString(). This patch adds the "+Inf" and "-Inf" strings to the list of recognized patterns in IEEEFloat::convertFromStringSpecials(). Re-landing after fix. Reviewers: sberg, bogner, majnemer, timshen, rnk, skatkov, gottesmm, bkramer, scanon, anna Reviewed By: anna Subscribers: mkazantsev, FlameTop, llvm-commits, reames, apilipenko Differential Revision: https://reviews.llvm.org/D38030 llvm-svn: 321054
* [TableGen][GlobalISel] Reset the internal map of RuleMatchers just before ↵Quentin Colombet2017-12-191-3/+4
| | | | | | | | | | | | | | | | | | | the emission Between the creation of the last InstructionMatcher and the first emission of the related Rule, we need to clear the internal map of IDs. We used to do that right after the creation of the main InstructionMatcher when building the rule and although that worked, this is fragile because if for some reason some later code decides to create more InstructionMatcher before the final call to emit, then the IDs would be completely messed up. Move that to the beginning of "emit" so that the IDs are guarantee to be consistent. NFC. llvm-svn: 321053
* Fix Wasm as a follow up to r321035 and the other oneReid Kleckner2017-12-191-1/+7
| | | | | | | This array is tightly coupled with the .def file. Someone should look into fixing that. llvm-svn: 321050
* update_mir_test_checks: Accept IR as input as well as MIRJustin Bogner2017-12-192-47/+93
| | | | | | | | We need to handle IR for tests that want to do lowering (or just -stop-after with IR as input). I've run this on one AArch64 test to demonstrate what it looks like. llvm-svn: 321048
* [llvm-objcopy] Add option to add a progbits section from a fileJake Ehrlich2017-12-195-1/+121
| | | | | | | | This change adds support for adding progbits sections with contents from a file Differential Revision: https://reviews.llvm.org/D41212 llvm-svn: 321047
* TargetLoweringBase: Followup to r321035Matthias Braun2017-12-193-25/+34
| | | | | | | | | I missed some prefixes and the fact that on AArch64 we use "bzero" instead of "__bzero" as on X86 when doing my refactoring in r321035. Improve tests for bzero. llvm-svn: 321046
* TargetLowering: Fix InitLibcallCallingConvs() overriding things set in ↵Matthias Braun2017-12-191-7/+3
| | | | | | | | | | | | | InitLibcalls() I missed the fact that the later called InitLibcallCallingConvs() overrides some things set in InitLibcalls() when I did the refactoring in r321036. Fix by merging InitLibcallCallingConvs() into InitLibcalls() and doing the initialization earlier. llvm-svn: 321045
* TargetLowering: Fix off-by-one errorMatthias Braun2017-12-191-1/+1
| | | | | | | This problem was present for a while, but somehow asan didn't catch it before the refactoring in r321036. llvm-svn: 321043
* [llvm-readobj] Dump wasm init functionsSam Clegg2017-12-191-2/+8
| | | | llvm-svn: 321042
* TargetLoweringBase: Remove unnecessary watchos exception; NFCMatthias Braun2017-12-181-3/+4
| | | | | | | WatchOS isn't report as iOS (as opposed to tvos) so the exception I added in my last commit wasn't necessary after all. llvm-svn: 321041
* update_mir_test_checks: Add "mir" to some states and regex namesJustin Bogner2017-12-181-16/+16
| | | | | | | For tests that do lowering we need to support IR as input, so here we clarify some names to avoid ambiguity in upcoming commits. llvm-svn: 321039
* [X86] Don't use NOPL when the assembler is passed an empty CPU string.Craig Topper2017-12-181-1/+1
| | | | | | This recommits the change from r321026. I have a fix for the lld test now. llvm-svn: 321038
* LiveStacks: Rename LiveStack.{h|cpp} to LiveStacks.{h|cpp}; NFCMatthias Braun2017-12-1811-15/+15
| | | | | | Filenames should match the name of the class they contain. llvm-svn: 321037
* X86/AArch64/ARM: Factor out common sincos_stret logic; NFCIMatthias Braun2017-12-1810-72/+62
| | | | | | | | | | | Note: - X86ISelLowering: setLibcallName(SINCOS) was superfluous as InitLibcalls() already does it. - ARMISelLowering: Setting libcallnames for sincos/sincosf seemed superfluous as in the darwin case it wouldn't be used while for all other cases InitLibcalls already does it. llvm-svn: 321036
* AArch64/X86: Factor out common bzero logic; NFCMatthias Braun2017-12-188-47/+13
| | | | llvm-svn: 321035
* [Hexagon] Cache loads to select to avoid traversing mutating DAGKrzysztof Parzyszek2017-12-182-12/+61
| | | | llvm-svn: 321034
* Revert part of r321026 "[X86] Don't use NOPL when the assembler is passed an ↵Craig Topper2017-12-181-1/+1
| | | | | | | | empty CPU string." while I investigate how to fix an lld test failure. Looks like lld also needs to pass a -mcpu in some of its tests llvm-svn: 321033
* [AArch64] Expand test coverage of vector element shuffling to ExynosEvandro Menezes2017-12-181-534/+151
| | | | | | Make sure that all test cases are run for Exynos as well. Otherwise, NFC. llvm-svn: 321032
* [TableGen][GlobalISel] Make the arguments of the Instruction and Operand ↵Quentin Colombet2017-12-181-18/+18
| | | | | | | | | | | | Matchers consistent Move InsnVarID and OpIdx at the beginning of the list of arguments for all the constructors of the OperandMatcher subclasses. This matches what we do for the InstructionMatcher. NFC. llvm-svn: 321031
* Fix buffer overrun in WindowsResourceCOFFWriter::writeSymbolTable()Bob Haarman2017-12-183-37/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: We were using sprintf(..., "$R06X", <some uint32_t>) to create strings that are expected to be exactly length 8, but this results in longer strings if the uint32_t is greater than 0xffffff. This change modifies the behavior as follows: - Uses the loop counter instead of the data offset. This gives us sequential symbol names, avoiding collisions as much as possible. - Masks the value to 0xffffff to avoid generating names longer than 8 bytes. - Uses formatv instead of sprintf. Fixes PR35581. Reviewers: ruiu, zturner Reviewed By: ruiu Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D41270 llvm-svn: 321030
* Add test for .req directive starting with 'p'Reid Kleckner2017-12-181-0/+5
| | | | | | Reduced test case from libjpeg_turbo. llvm-svn: 321029
* [MachineOutliner][NFC] Gardening: use std::any_of instead of bool + loopJessica Paquette2017-12-181-10/+3
| | | | | | | River Riddle suggested to use std::any_of instead of the bool + loop thing on r320229. This commit does that. llvm-svn: 321028
* [X86] Don't use NOPL when the assembler is passed an empty CPU string. ↵Craig Topper2017-12-1813-24/+24
| | | | | | | | | | Update tests to force a CPU with NOPL Empty string should be equivalent to "generic" which doesn't allow NOPL. Force tests to use specificy 'pentiumpro' to guarantee NOPL. Fixes PR35686 llvm-svn: 321026
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