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author | Simon Dardis <simon.dardis@mips.com> | 2017-12-19 11:16:22 +0000 |
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committer | Simon Dardis <simon.dardis@mips.com> | 2017-12-19 11:16:22 +0000 |
commit | 1ade566c451c1aa7f0dc70d2a4e37874d5105c2c (patch) | |
tree | 883fa7e6ee50fd37e6ca0cdd688641f3ecb07c3b /llvm | |
parent | 800d4371f31a80fd7cba643257191955c68e2444 (diff) | |
download | bcm5719-llvm-1ade566c451c1aa7f0dc70d2a4e37874d5105c2c.tar.gz bcm5719-llvm-1ade566c451c1aa7f0dc70d2a4e37874d5105c2c.zip |
[mips] Handle the emission of microMIPSr6 sll instruction when used as a nop.
This instruction is encoded as zero, so we have handle that case when checking
for unimplemented opcodes when producing the encoding for an instruction.
llvm-svn: 321066
Diffstat (limited to 'llvm')
-rw-r--r-- | llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | 2 | ||||
-rw-r--r-- | llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir | 46 |
2 files changed, 47 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp index ac81e620745..2f6dd0035de 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -188,7 +188,7 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS, // so we have to special check for them. unsigned Opcode = TmpInst.getOpcode(); if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && - (Opcode != Mips::SLL_MM) && !Binary) + (Opcode != Mips::SLL_MM) && (Opcode != Mips::SLL_MMR6) && !Binary) llvm_unreachable("unimplemented opcode in encodeInstruction()"); int NewOpcode = -1; diff --git a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir new file mode 100644 index 00000000000..85ce251ac31 --- /dev/null +++ b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir @@ -0,0 +1,46 @@ +# RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips %s -start-after=xray-instrumentation -o - -show-mc-encoding | FileCheck %s + +# Test that the 'sll $zero, $zero, 0' is correctly recognized as a real +# instruction rather than some unimplemented opcode for the purposes of +# encoding an instruction. + +# CHECK-LABEL: a: +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK: jrc $ra # encoding: [0x45,0xbf] +--- +name: a +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: false +registers: +liveins: + - { reg: '%a0', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + renamable %zero = SLL_MMR6 killed renamable %zero, 0 + JRC16_MM undef %ra, implicit %v0 + +... |