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* Minor code simplification.Dan Gohman2010-05-271-9/+9
| | | | llvm-svn: 104845
* AsmMatcher: Ensure classes are totally ordered, so we can std::sort them ↵Daniel Dunbar2010-05-271-1/+10
| | | | | | reliably. llvm-svn: 104806
* Check that inherited subregisters all have a direct SubRegIndex.Jakob Stoklund Olesen2010-05-261-2/+25
| | | | llvm-svn: 104755
* Add StringRef::compare_numeric and use it to sort TableGen register records.Jakob Stoklund Olesen2010-05-262-1/+3
| | | | | | | This means that our Registers are now ordered R7, R8, R9, R10, R12, ... Not R1, R10, R11, R12, R2, R3, ... llvm-svn: 104745
* Suppress emmission of empty subreg/superreg/alias sets.Jakob Stoklund Olesen2010-05-261-3/+9
| | | | llvm-svn: 104741
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-36/+83
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. llvm-svn: 104704
* Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen2010-05-261-83/+36
| | | | | | This reverts commit 104654. llvm-svn: 104660
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-36/+83
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. llvm-svn: 104654
* Drop the SuperregHashTable. It is essentially the same as SubregHashTable.Jakob Stoklund Olesen2010-05-251-84/+5
| | | | llvm-svn: 104650
* Print symbolic SubRegIndex names on machine operands.Jakob Stoklund Olesen2010-05-251-1/+12
| | | | llvm-svn: 104628
* Ignore NumberHack and give each SubRegIndex instance a unique enum value ↵Jakob Stoklund Olesen2010-05-252-3/+6
| | | | | | | | | | | instead. This passes lit tests, but I'll give it a go through the buildbots to smoke out any remaining places that depend on the old SubRegIndex numbering. Then I'll remove NumberHack entirely. llvm-svn: 104615
* Switch SubRegSet to using symbolic SubRegIndicesJakob Stoklund Olesen2010-05-241-6/+9
| | | | llvm-svn: 104571
* diaggroup categories should take precedence over diag-specific groups.Chris Lattner2010-05-241-8/+9
| | | | llvm-svn: 104567
* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-244-82/+114
| | | | | | | | | | | structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. llvm-svn: 104563
* Add the SubRegIndex TableGen class.Jakob Stoklund Olesen2010-05-244-12/+46
| | | | | | | This is the beginning of purely symbolic subregister indices, but we need a bit of jiggling before the explicit numeric indices can be completely removed. llvm-svn: 104492
* tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses ↵Daniel Dunbar2010-05-221-4/+8
| | | | | | instead of just one. llvm-svn: 104452
* tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honorDaniel Dunbar2010-05-201-0/+4
| | | | | | it. llvm-svn: 104270
* lit: Add another place to look for bash.Daniel Dunbar2010-05-191-1/+1
| | | | llvm-svn: 104189
* Replace FIRST_* and LAST_* macros with a generic STMT_RANGE macroAlexis Hunt2010-05-181-20/+27
| | | | | | Also rename ABSTRACT to ABSTRACT_STMT llvm-svn: 104018
* Added a QQQQ register file to model 4-consecutive Q registers.Evan Cheng2010-05-141-0/+1
| | | | llvm-svn: 103760
* Adding a v8i64 512-bit vector type. This will be used to model ARM NEON ↵Evan Cheng2010-05-131-0/+1
| | | | | | intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers. llvm-svn: 103746
* Update tablegen to generate shorts instead of chars for subgroup arrays.Chandler Carruth2010-05-131-1/+1
| | | | llvm-svn: 103704
* lit: Fix a sh lexing bug which caused annotate-token.m to fail when run with theDaniel Dunbar2010-05-121-0/+7
| | | | | | | | | | internal shell parser; we weren't lexing the quotes in a command like:: clang -DFOO='hello' correctly. llvm-svn: 103652
* lit: Fix OneCommandPerFileTest format when tests are specified directly.Daniel Dunbar2010-05-121-1/+3
| | | | llvm-svn: 103626
* lit: Add support for 'lit ... @foo', which reads a list of tests to run fromDaniel Dunbar2010-05-121-1/+17
| | | | | | foo. llvm-svn: 103625
* Add initial kill flag support to FastISel.Dan Gohman2010-05-111-5/+5
| | | | llvm-svn: 103529
* Fixes for Microsoft Visual Studio 2010, from Steven Watanabe!Douglas Gregor2010-05-112-0/+22
| | | | llvm-svn: 103457
* Eliminated the classification of control registers into %ecr_Sean Callanan2010-05-062-6/+3
| | | | | | | | | and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. llvm-svn: 103196
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-2/+2
| | | | | | doesn't have to guess. llvm-svn: 103194
* Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a ↵Evan Cheng2010-05-061-2/+3
| | | | | | coalescer bug that's fixed by 103170. llvm-svn: 103172
* Fix some stylistic issues with my last commit.Alexis Hunt2010-05-062-78/+86
| | | | llvm-svn: 103164
* Select an ARM-hosted cross build with a separate makefile target instead ofBob Wilson2010-05-052-29/+31
| | | | | | a magic project name. llvm-svn: 103125
* Rearrange the suppressions files to be by-architecture instead of by-problem.Jeffrey Yasskin2010-05-053-23/+7
| | | | | | ddunbar says the gcc-4.3.3 suppressions are obsolete. llvm-svn: 103106
* Add a suppressions file for an intermittent "leak" under RegisterPass.Jeffrey Yasskin2010-05-051-0/+7
| | | | llvm-svn: 103100
* lit: Allow test_format to be None.Daniel Dunbar2010-05-051-3/+4
| | | | llvm-svn: 103091
* Add newline to end of file to avoid warningShantonu Sen2010-05-051-1/+1
| | | | | | when building llvm with clang llvm-svn: 103084
* Include the right header for toupperAlexis Hunt2010-05-051-1/+1
| | | | llvm-svn: 103073
* Add an emitter to handle the list of clang statement nodes.Alexis Hunt2010-05-055-12/+182
| | | | llvm-svn: 103071
* add the ability to associate 'category' names with clang diagnosticsChris Lattner2010-05-041-3/+118
| | | | | | | | | and diagnostic groups. This allows the compiler to group diagnostics together (e.g. "Logic Warning", "Format String Warning", etc) like the static analyzer does. This is not exposed through anything in the compiler yet. llvm-svn: 103050
* MC/Matcher: Add support for over-riding the default MatchInstruction functionDaniel Dunbar2010-05-041-4/+8
| | | | | | | name (for example, to allow targets to interpose the actual MatchInstruction function). llvm-svn: 102987
* Add a polygen rule that reflects the fact that nsw and nuw can beDan Gohman2010-05-041-1/+1
| | | | | | used together in either order. llvm-svn: 102983
* Remove special case for llvmCore_Embedded project. This is no longer neededBob Wilson2010-05-031-5/+0
| | | | | | since llvmCore is built as part of llvmgcc42 now. llvm-svn: 102962
* Add a pseudo instruction REG_SEQUENCE that takes a list of registers andEvan Cheng2010-05-012-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sub-register indices and outputs a single super register which is formed from a consecutive sequence of registers. This is used as register allocation / coalescing aid and it is useful to represent instructions that output register pairs / quads. For example, v1024, v1025 = vload <address> where v1024 and v1025 forms a register pair. This really should be modelled as v1024<3>, v1025<4> = vload <address> but it would violate SSA property before register allocation is done. Currently we use insert_subreg to form the super register: v1026 = implicit_def v1027 - insert_subreg v1026, v1024, 3 v1028 = insert_subreg v1027, v1025, 4 ... = use v1024 = use v1028 But this adds pseudo live interval overlap between v1024 and v1025. We can now modeled it as v1024, v1025 = vload <address> v1026 = REG_SEQUENCE v1024, 3, v1025, 4 ... = use v1024 = use v1026 After coalescing, it will be v1026<3>, v1025<4> = vload <address> ... = use v1026<3> = use v1026 llvm-svn: 102815
* Don't remove libLTO.dylib if it's not being installed in Developer/usr/lib;Bob Wilson2010-04-291-2/+0
| | | | | | just leave it in Developer/usr/local/lib. llvm-svn: 102646
* Add an option to the Apple-style build to control whether libLTO.dylib shouldBob Wilson2010-04-282-12/+24
| | | | | | be installed. Disable it by default. llvm-svn: 102531
* Undo most of my previous whitespace fix. I think I like it better this wayBob Wilson2010-04-281-3/+3
| | | | | | after all. llvm-svn: 102508
* Fix inconsistent use of HOSTS and TARGETS variables.Bob Wilson2010-04-281-3/+3
| | | | llvm-svn: 102505
* Fix whitespace.Bob Wilson2010-04-281-4/+3
| | | | llvm-svn: 102504
* Fixes to edis that mark x86 call targets asSean Callanan2010-04-231-2/+2
| | | | | | memory operands rather than immediate operands. llvm-svn: 102217
* When doing Thumb disassembly, there's no need to consider ↵Johnny Chen2010-04-201-3/+6
| | | | | | | | t2ADDrSPi12/t2SUBrSPi12, as their generic counterparts t2ADDri12/t2SUBri12 should suffice. llvm-svn: 101929
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