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* TableGen subtarget emitter. Generate resolveSchedClass generated hook for ↵Andrew Trick2012-09-181-0/+84
| | | | | | resolving instruction variants. llvm-svn: 164095
* TableGen subtarget emitter. Remove unnecessary header dependence.Andrew Trick2012-09-181-0/+1
| | | | llvm-svn: 164094
* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-181-6/+25
| | | | | | model. llvm-svn: 164092
* Mark asm matcher conversion table as const.Craig Topper2012-09-181-5/+5
| | | | llvm-svn: 164088
* Fix typo in comment. No functional change.Craig Topper2012-09-181-1/+1
| | | | llvm-svn: 164086
* Backout the wrong subtarget emitter fixAndrew Trick2012-09-171-1/+1
| | | | llvm-svn: 164078
* Fix release build after revertingAndrew Trick2012-09-171-2/+1
| | | | llvm-svn: 164075
* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-173-113/+20
| | | | | | | I have to work out the Target/CodeGen header dependencies before putting this back. llvm-svn: 164072
* InitMCProcessorAndrew Trick2012-09-171-1/+2
| | | | llvm-svn: 164066
* comment typoAndrew Trick2012-09-171-1/+1
| | | | llvm-svn: 164064
* TableGen subtarget emitter. Use getSchedClassIdx.Andrew Trick2012-09-172-11/+1
| | | | llvm-svn: 164063
* TableGen subtarget emitter. Generate resolveSchedClass generated hook for ↵Andrew Trick2012-09-171-0/+84
| | | | | | resolving instruction variants. llvm-svn: 164062
* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-171-7/+25
| | | | | | model. llvm-svn: 164061
* TableGen subtarget emitter. Format and emit data tables for the new machine ↵Andrew Trick2012-09-171-6/+117
| | | | | | model. llvm-svn: 164060
* TableGen subtarget emitter. Generate data tables for the new machine model.Andrew Trick2012-09-171-2/+291
| | | | | | | | | | | | Map the CodeGenSchedule object model onto data tables. The structure of the data tables is defined in MC, so for convenience we include MCSchedule.h. The alternative is maintaining a redundant copy of the table structure definitions. Mapping the object model onto data tables is sufficiently complicated that it should not be interleaved with emitting source code. This avoids major problem with the backend for itinerary generation. llvm-svn: 164059
* TableGen subtarget emitter. Emit processor resources for the new machine model.Andrew Trick2012-09-171-10/+63
| | | | llvm-svn: 164058
* TableGen subtarget parser: Add getProcResourcesIdx().Andrew Trick2012-09-171-0/+10
| | | | llvm-svn: 164057
* TableGen: Add initializer.Jim Grosbach2012-09-171-1/+1
| | | | | | | Keep GCC's warnings happy. It can't reason out that the state machine won't ever hit the potentially uninitialized use in OPC_FilterValue. llvm-svn: 164041
* Fix a few vars that can end up being used without initialization.Axel Naumann2012-09-171-1/+1
| | | | | | The cases where no initialization happens should still be checked for logic flaws. llvm-svn: 164032
* Fix typoMichael Liao2012-09-171-1/+1
| | | | llvm-svn: 164012
* Add 'virtual' keywoards to output file for overridden functions.Craig Topper2012-09-161-5/+6
| | | | llvm-svn: 164002
* Add 'virtual' keywoards to output file for overridden functions.Craig Topper2012-09-161-7/+7
| | | | llvm-svn: 163999
* Fix Doxygen issues: wrap code examples in \code and use \p to refer toDmitri Gribenko2012-09-151-4/+4
| | | | | | parameters. llvm-svn: 163984
* Revert r163878 as it breaks on targets with alternate register names. Such ↵Craig Topper2012-09-152-6/+4
| | | | | | targets do not exist in the main tree so this was not noticed. llvm-svn: 163959
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-152-0/+219
| | | | | | Collect processor resources from the subtarget defs. llvm-svn: 163953
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-152-0/+512
| | | | | | Infer SchedClasses from variants defined by the target or subtarget. llvm-svn: 163952
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-153-137/+816
| | | | | | Collect SchedClasses and SchedRW types from the subtarget defs. llvm-svn: 163951
* Allow the second opcode info table to be 8, 16, or 32-bits as needed to ↵Craig Topper2012-09-141-38/+32
| | | | | | represent additional fragments. This recovers some space on ATT X86 syntax and PowerPC which only need 40-bits instead of 48-bits. This also increases ARM to 64-bits to fully encode all of its operands. llvm-svn: 163880
* Reduce size of register name index tables by using uint16_t for all in tree ↵Craig Topper2012-09-142-4/+6
| | | | | | targets. If more than 16-bits are needed for any out of tree targets, code will detect and use uint32_t instead. llvm-svn: 163878
* AsmWriterEmitter: OpInfo2 should be unsigned 16-bit.Manman Ren2012-09-131-1/+1
| | | | | | Fix an issue in r163814. llvm-svn: 163837
* AsmWriterEmitter: increase the number of bits for OpcodeInfo from 32-bit toManman Ren2012-09-131-11/+46
| | | | | | | | | | | 48-bit if necessary, in order to reduce the generated code size. We have 900 cases not covered by OpcodeInfo in ATT AsmWriter and more in Intel AsmWriter and ARM AsmWriter. This patch reduced the clang Release build size by 50k, running on a Mac Pro. llvm-svn: 163814
* Fix Doxygen issues:Dmitri Gribenko2012-09-132-20/+21
| | | | | | | | * wrap code blocks in \code ... \endcode; * refer to parameter names in paragraphs correctly (\arg is not what most people want -- it starts a new paragraph). llvm-svn: 163790
* Add a new compression type to ModRM table that detects when the memory modRM ↵Craig Topper2012-09-131-2/+15
| | | | | | byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. llvm-svn: 163774
* TableGen: Convert an assert() to a proper diagnostic.Jim Grosbach2012-09-121-1/+3
| | | | llvm-svn: 163726
* Fix a couple of Doxygen comment issues pointed out by -Wdocumentation.Dmitri Gribenko2012-09-121-20/+21
| | | | llvm-svn: 163721
* Improve tblgen code cleanliness: create an unknown_class, from which the ↵Owen Anderson2012-09-112-3/+3
| | | | | | unknown def inherits. Make tblgen check for that class, rather than checking for the def itself. llvm-svn: 163664
* Compute a map from register names to registers, rather than scanning the ↵Owen Anderson2012-09-113-6/+15
| | | | | | list of registers every time we want to look up a register by name. llvm-svn: 163659
* Add TRI::getSubRegIndexLaneMask().Jakob Stoklund Olesen2012-09-113-6/+68
| | | | | | | | | | | | | | | | | Sub-register lane masks are bitmasks that can be used to determine if two sub-registers of a virtual register will overlap. For example, ARM's ssub0 and ssub1 sub-register indices don't overlap each other, but both overlap dsub0 and qsub0. The lane masks will be accurate on most targets, but on targets that use sub-register indexes in an irregular way, the masks may conservatively report that two sub-register indices overlap when the eventually allocated physregs don't. Irregular register banks also mean that the bits in a lane mask can't be mapped onto register units, but the concept is similar. llvm-svn: 163630
* Clean the sub-reg index composition maps at emission.Jakob Stoklund Olesen2012-09-113-20/+2
| | | | | | | Preserve the Composites map in the CodeGenSubRegIndex class so it can be used to determine which sub-register indices can actually be composed. llvm-svn: 163629
* Add MCRI::getNumSubRegIndices() and start checking SubRegIndex ranges.Jakob Stoklund Olesen2012-09-111-2/+2
| | | | | | | | Apparently, NumSubRegIndices was completely unused before. Adjust it by one to include the null subreg index, just like getNumRegs() includes the null register. llvm-svn: 163628
* Change unsigned to a uint16_t in static disassembler tables to reduce the ↵Craig Topper2012-09-111-0/+4
| | | | | | table size. llvm-svn: 163594
* GTest on Android needs a custom tmpdir path.Evgeniy Stepanov2012-09-101-0/+4
| | | | llvm-svn: 163501
* lit: Util.which(): Use os.path.isfile() instead of os.path.exists(), or it ↵NAKAMURA Takumi2012-09-081-1/+1
| | | | | | | | hits to the directory. For example, which('loop-convert') returns 'loop-convert' when the directory 'loop-convert' exists. llvm-svn: 163469
* Revert "Add -exact-match option to FileCheck to allow clients to do exact ↵Ted Kremenek2012-09-081-5/+1
| | | | | | | | | matches without using regular expressions." Turns out I did not need it after all. If we find a use for it in the future, we can resurrect it. llvm-svn: 163457
* Refactored DFA generator. Merged transition class into state class.Anshuman Dasgupta2012-09-071-117/+51
| | | | | | Patch by Ivan Llopard! llvm-svn: 163424
* Add -exact-match option to FileCheck to allow clients to do exact matches ↵Ted Kremenek2012-09-071-1/+5
| | | | | | without using regular expressions. llvm-svn: 163371
* Re-work bit/bits value resolving in tblgenMichael Liao2012-09-062-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - This patch is inspired by the failure of the following code snippet which is used to convert enumerable values into encoding bits to improve the readability of td files. class S<int s> { bits<2> V = !if(!eq(s, 8), {0, 0}, !if(!eq(s, 16), {0, 1}, !if(!eq(s, 32), {1, 0}, !if(!eq(s, 64), {1, 1}, {?, ?})))); } Later, PR8330 is found to report not exactly the same bug relevant issue to bit/bits values. - Instead of resolving bit/bits values separately through resolveBitReference(), this patch adds getBit() for all Inits and resolves bit value by resolving plus getting the specified bit. This unifies the resolving of bit with other values and removes redundant logic for resolving bit only. In addition, BitsInit::resolveReferences() is optimized to take advantage of this origanization by resolving VarBitInit's variable reference first and then getting bits from it. - The type interference in '!if' operator is revised to support possible combinations of int and bits/bit in MHS and RHS. - As there may be illegal assignments from integer value to bit, says assign 2 to a bit, but we only check this during instantiation in some cases, e.g. bit V = !if(!eq(x, 17), 0, 2); Verbose diagnostic message is generated when invalid value is resolveed to help locating the error. - PR8330 is fixed as well. llvm-svn: 163360
* Tablegen: Add OperandWithDefaultOps Operand typeTom Stellard2012-09-064-52/+41
| | | | | | | This Operand type takes a default argument, and is initialized to this value if it does not appear in a patter. llvm-svn: 163315
* Add a new optimization pass: Stack Coloring, that merges disjoint static ↵Nadav Rotem2012-09-061-0/+2
| | | | | | | | allocations (allocas). Allocas are known to be disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics). llvm-svn: 163299
* Constify subtarget info properly so that we dont cast away the const inRoman Divacky2012-09-051-1/+1
| | | | | | the SubtargetInfoKV tables. Found by gcc48 -Wcast-qual. llvm-svn: 163251
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