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| author | Craig Topper <craig.topper@gmail.com> | 2012-09-16 16:35:22 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-09-16 16:35:22 +0000 |
| commit | 8dcaf4998cb49b01e4cb8e98b3499e3110e418da (patch) | |
| tree | 743574c5d6af4bc4ef800f03c3bd0fb983708e14 /llvm/utils | |
| parent | ae6809b19a8ccb54cb234f7aceb3b049a4abacbb (diff) | |
| download | bcm5719-llvm-8dcaf4998cb49b01e4cb8e98b3499e3110e418da.tar.gz bcm5719-llvm-8dcaf4998cb49b01e4cb8e98b3499e3110e418da.zip | |
Add 'virtual' keywoards to output file for overridden functions.
llvm-svn: 163999
Diffstat (limited to 'llvm/utils')
| -rw-r--r-- | llvm/utils/TableGen/RegisterInfoEmitter.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp index 42b213c04ac..87624665cbc 100644 --- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp +++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp @@ -802,16 +802,16 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, << " virtual bool needsStackRealignment(const MachineFunction &) const\n" << " { return false; }\n"; if (!RegBank.getSubRegIndices().empty()) { - OS << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n" - << " const TargetRegisterClass *" + OS << " virtual unsigned composeSubRegIndices(unsigned, unsigned) const;\n" + << " virtual const TargetRegisterClass *" "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"; } - OS << " const RegClassWeight &getRegClassWeight(" + OS << " virtual const RegClassWeight &getRegClassWeight(" << "const TargetRegisterClass *RC) const;\n" - << " unsigned getNumRegPressureSets() const;\n" - << " const char *getRegPressureSetName(unsigned Idx) const;\n" - << " unsigned getRegPressureSetLimit(unsigned Idx) const;\n" - << " const int *getRegClassPressureSets(" + << " virtual unsigned getNumRegPressureSets() const;\n" + << " virtual const char *getRegPressureSetName(unsigned Idx) const;\n" + << " virtual unsigned getRegPressureSetLimit(unsigned Idx) const;\n" + << " virtual const int *getRegClassPressureSets(" << "const TargetRegisterClass *RC) const;\n" << "};\n\n"; |
