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* Use pass-by-reference for-range loop. NFCI.Simon Pilgrim2018-09-181-2/+3
| | | | llvm-svn: 342481
* Fix signed/unsigned comparison warning. NFCI.Simon Pilgrim2018-09-181-1/+1
| | | | llvm-svn: 342469
* [TableGen] CodeGenDAGPatterns::GenerateVariants - full caching of matching ↵Simon Pilgrim2018-09-181-11/+49
| | | | | | | | | | | | predicates Further extension to D51035, this patch avoids all repeated predicates[] matching by caching as it collects the patterns that have multiple variants. Saves around 25secs in debug builds of x86 -gen-dag-isel. Differential Revision: https://reviews.llvm.org/D51839 llvm-svn: 342467
* Test commit: remove trailing whitespaceJosh Stone2018-09-112-4/+4
| | | | llvm-svn: 341966
* [WebAssembly] Made disassembler only use stack instructions.Wouter van Oortmerssen2018-08-301-15/+46
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Now uses the StackBased bit from the tablegen defs to identify stack instructions (and ignore register based or non-wasm instructions). Also changed how we store operands, since we now have up to 16 of them per instruction. To not cause static data bloat, these are compressed into a tiny table. + a few other cleanups. Tested: - MCTest - llvm-lit -v `find test -name WebAssembly` Reviewers: dschuff, jgravelle-google, sunfish, tlively Subscribers: sbc100, aheejin, llvm-commits Differential Revision: https://reviews.llvm.org/D51320 llvm-svn: 341081
* Remove debug code accidently committed in rL340837. NFCI.Simon Pilgrim2018-08-291-3/+0
| | | | llvm-svn: 340908
* [WebAssembly][NFC] Document stackifier tablegen backendThomas Lively2018-08-281-1/+12
| | | | | | | | | | | | | | Summary: Add comments to help readers avoid having to read tablegen backends to understand the code. Also remove unecessary breaks from the output. Reviewers: dschuff, aheejin Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51371 llvm-svn: 340864
* [WebAssembly][NFC] Fix formatting from rL340781Thomas Lively2018-08-281-2/+4
| | | | | | | | | | Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51367 llvm-svn: 340861
* [TableGen] CodeGenDAGPatterns::GenerateVariants - basic caching of matching ↵Simon Pilgrim2018-08-281-2/+14
| | | | | | | | | | | | | | predicates CodeGenDAGPatterns::GenerateVariants is a costly function in many tblgen commands (33.87% of the total runtime of x86 -gen-dag-isel), and due to the O(N^2) nature of the function, there are a high number of repeated comparisons of the pattern's vector<Predicate>. This initial patch at least avoids repeating these comparisons for every Variant in a pattern. I began investigating caching all the matches before entering the loop but hit issues with how best to store the data and how to update the cache as patterns were added. Saves around 15secs in debug builds of x86 -gen-dag-isel. Differential Revision: https://reviews.llvm.org/D51035 llvm-svn: 340837
* [TableGen] Use std::move where possible in InstructionMemo constructor. NFCI.Simon Pilgrim2018-08-281-6/+6
| | | | | | Requested in post-commit review for rL339670 llvm-svn: 340819
* [WebAssembly] TableGen backend for stackifying instructionsThomas Lively2018-08-274-1/+40
| | | | | | | | | | | | | | | | | Summary: The new stackification backend generates the giant switch statement used to translate instructions to their stackified forms. I did this because it was more interesting than adding all the different vector versions of the various SIMD instructions to the switch statment manually. Reviewers: aardappel, aheejin, dschuff Subscribers: mgorny, sbc100, jgravelle-google, sunfish, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D51318 llvm-svn: 340781
* TableGen/SearchableTables: Cast enums to unsigned in generated codeNicolai Haehnle2018-08-231-0/+9
| | | | | | | | | | | | | | | Summary: This should fix signedness warnings when compiling with MSVC. Change-Id: I4664cce0ba91e9b42d21a86fd4a7e82f2320c451 Reviewers: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D51097 llvm-svn: 340518
* [WebAssembly] Add isEHScopeReturn instruction propertyHeejin Ahn2018-08-214-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Summary: So far, `isReturn` property is used to mean both a return instruction from a functon and the end of an EH scope, a scope that starts with a EH scope entry BB and ends with a catchret or a cleanupret instruction. Because WinEH uses funclets, all EH-scope-ending instructions are also real return instruction from a function. But for wasm, they only serve as the end marker of an EH scope but not a return instruction that exits a function. This mismatch caused incorrect prolog and epilog generation in wasm EH scopes. This patch fixes this. This patch is in the same vein with rL333045, which splits `MachineBasicBlock::isEHFuncletEntry` into `isEHFuncletEntry` and `isEHScopeEntry`. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50653 llvm-svn: 340325
* [TableGen] Don't separately search for DefaultMode when we're going to ↵Simon Pilgrim2018-08-171-1/+3
| | | | | | iterate the set anyway. NFCI. llvm-svn: 340055
* [TableGen] TypeInfer - Cache the legal types as TypeSetByHwModeSimon Pilgrim2018-08-172-18/+13
| | | | | | | | | | | | We were just caching the MVT set of legal types, then every call creating a new TypeSetByHwMode with it and passing it back on the stack. There's no need to do this - we can create and cache the whole TypeSetByHwMode once and return a const reference to it each time. Additionally, TypeInfer::expandOverloads wasn't making use of the fact that the cache just contains a default mode containing all the types. Saves up to 30secs in debug builds of x86 -gen-dag-isel. Differential Revision: https://reviews.llvm.org/D50903 llvm-svn: 340042
* [TableGen] TypeSetByHwMode::insert - cache the default MVT. NFCI.Simon Pilgrim2018-08-171-3/+10
| | | | | | Avoids repeated count()/find() calls that we've already have the default values for. llvm-svn: 340020
* [TableGen] TypeSetByHwMode::operator== optimizationSimon Pilgrim2018-08-161-8/+10
| | | | | | | | | | | | | | This operator is called a great deal, by checking for the cheap isSimple equality cases first (a common occurrence) we can improve performance as we avoid a lot of std::map find/iteration in hasDefault. isSimple also means that a default value is present, so we can avoid some hasDefault calls. This also avoids a rather dodgy piece of logic that was checking for isSimple() && !VTS.isSimple() but not the inverse - it now uses the general hasDefault mode comparison test instead. Saves around 15secs in debug builds of x86 -gen-dag-isel. Differential Revision: https://reviews.llvm.org/D50841 llvm-svn: 339890
* [TableGen] Avoid self getPredicates() != comparison. NFCI.Simon Pilgrim2018-08-161-2/+2
| | | | | | We were performing a completely unnecessary full comparison of the same std::vector<Predicate>. llvm-svn: 339888
* [TableGen] Return ValueTypeByHwMode by const reference from ↵Simon Pilgrim2018-08-162-4/+4
| | | | | | | | CodeGenRegisterClass::getValueTypeNum Avoids costly std::map copies inside ValueTypeByHwMode constructor llvm-svn: 339884
* [TableGen] Remove unnecessary TypeSetByHwMode -> ValueTypeByHwMode -> ↵Simon Pilgrim2018-08-151-1/+1
| | | | | | | | | | | | | | TypeSetByHwMode conversions in getPatternSize I noticed this during profiling of tablegen (PR28222) that we were calling Child->getType(0) which creates a ValueTypeByHwMode on the fly from the requested internal TypeSetByHwMode type and returns it by value, we then treat it as a TypeSetByHwMode reference which involves constructing a new TypeSetByHwMode on the stack with a large amount of std::map iterating/copying all along the way. I am not an expert on tablegen, but AFAICT this is all unnecessary and we should be calling Child->getExtType(0) which returns the original TypeSetByHwMode by reference. This gives me a 90sec reduction in msvc debug builds of x86 -gen-dag-isel. Differential Revision: https://reviews.llvm.org/D50789 llvm-svn: 339812
* [Tablegen][MCInstPredicate] Removed redundant template argument from class ↵Andrea Di Biagio2018-08-146-24/+46
| | | | | | | | | | | | | | | | | | | | | | | | TIIPredicate, and implemented verification rules for TIIPredicates. This patch removes redundant template argument `TargetName` from TIIPredicate. Tablegen can always infer the target name from the context. So we don't need to force users of TIIPredicate to always specify it. This allows us to better modularize the tablegen class hierarchy for the so-called "function predicates". class FunctionPredicateBase has been added; it is currently used as a building block for TIIPredicates. However, I plan to reuse that class to model other function predicate classes too (i.e. not just TIIPredicates). For example, this can be a first step towards implementing proper support for dependency breaking instructions in tablegen. This patch also adds a verification step on TIIPredicates in tablegen. We cannot have multiple TIIPredicates with the same name. Otherwise, this will cause build errors later on, when tablegen'd .inc files are included by cpp files and then compiled. Differential Revision: https://reviews.llvm.org/D50708 llvm-svn: 339706
* [TableGen] Pass string/vector types by const reference (PR37666). NFCISimon Pilgrim2018-08-141-5/+6
| | | | llvm-svn: 339670
* [X86] Don't ignore 0x66 prefix on relative jumps in 64-bit mode. Fix opcode ↵Craig Topper2018-08-131-2/+2
| | | | | | | | | | | | | | | | selection of relative jumps in 16-bit mode. Treat jno/jo like other jcc instructions. The behavior in 64-bit mode is different between Intel and AMD CPUs. Intel ignores the 0x66 prefix. AMD does not. objump doesn't ignore the 0x66 prefix. Since LLVM aims to match objdump behavior, we should do the same. While I was trying to fix this I had change brtarget16/32 to use ENCODING_IW/ID instead of ENCODING_Iv to get the 0x66+REX.W case to act sort of sanely. It's still wrong, but that's a problem for another day. The change in encoding exposed the fact that 16-bit mode disassembly of relative jumps was creating JMP_4 with a 2 byte immediate. It should have been JMP_2. From just printing you can't tell the difference, but if you dumped the encoding it wouldn't have matched what we started with. While fixing that, it exposed that jo/jno opcodes were missing from the switch that this patch deleted and there were no test cases for them. Fixes PR38537. llvm-svn: 339622
* [Tablegen] Replace uses of formatted_raw_ostream with raw_ostream in the ↵Andrea Di Biagio2018-08-134-137/+134
| | | | | | | | | | | | | | | | | | | | | | predicate expander. NFCI This is a follow-up of r339552. As pointed out by Craig in D50566, we don't need a formatted_raw_ostream to indent strings. We can use instead raw_ostream::indent(). Internally, class PredicateExpander already keeps track of the current indentation level. Also, the grammar for predicates is well parenthesized, and therefore we don't need to use a formatted_raw_ostream to continuously track the column number. Instead we can safely replace all the uses of formatted_raw_ostream::PadToColumn() with uses of raw_ostream::indent(). By replacing formatted_raw_ostream with a simpler raw_ostream, we also avoid the implicit check on the newline character on every print to stream. No functional change intended. llvm-svn: 339577
* [Tablegen][SubtargetEmitter] Improve expansion of predicates of a variant ↵Andrea Di Biagio2018-08-131-15/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | scheduling class. This patch refactors the logic that expands predicates of a variant scheduling class. The idea is to improve the readability of the auto-generated code by removing redundant parentheses around predicate expressions, and by removing redundant if(true) statements. This patch replaces the definition of NoSchedPred in TargetSchedule.td with an instance of MCSchedPredicate. The new definition is sematically equivalent to the previous one. The main difference is that now SubtargetEmitter knows that it represents predicate "true". Before this patch, we always generated an if (true) for the default transition of a variant scheduling class. Example (taken from AArch64GenSubtargetInfo.inc) : ``` if (SchedModel->getProcessorID() == 3) { // CycloneModel if ((TII->isScaledAddr(*MI))) return 927; // (WriteIS_WriteLD)_ReadBaseRS if ((true)) return 928; // WriteLD_ReadDefault } ``` Extra parentheses were also generated around the predicate expressions. With this patch, we get the following auto-generated checks: ``` if (SchedModel->getProcessorID() == 3) { // CycloneModel if (TII->isScaledAddr(*MI)) return 927; // (WriteIS_WriteLD)_ReadBaseRS return 928; // WriteLD_ReadDefault } ``` The new auto-generated code behaves exactly the same as before. So, technically this is a non functional change. Differential revision: https://reviews.llvm.org/D50566 llvm-svn: 339552
* [globalisel] Remove dead code from GlobalISelEmitterDaniel Sanders2018-08-121-17/+0
| | | | | | | | | | | | | | | | Summary: Found by GCC's -Wunused-function. Patch by Kim Gräsman Reviewers: ab, dsanders, llvm-commits Reviewed By: dsanders Subscribers: rovka, kristof.beyls Differential Revision: https://reviews.llvm.org/D50611 llvm-svn: 339528
* [Tablegen][SubtargetEmitter] refactor method `emitSchedModelHelpersImpl()`. NFCIAndrea Di Biagio2018-08-101-62/+96
| | | | | | | | | | Part of the logic has been moved to helper functions to (hopefully) improve readability. Added a few code comments to better describe how the algorithm works. No functional change intended. llvm-svn: 339421
* [MC][PredicateExpander] Extend the grammar to support simple switch and ↵Andrea Di Biagio2018-08-093-6/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | return statements. This patch introduces tablegen class MCStatement. Currently, an MCStatement can be either a return statement, or a switch statement. ``` MCStatement: MCReturnStatement MCOpcodeSwitchStatement ``` A MCReturnStatement expands to a return statement, and the boolean expression associated with the return statement is described by a MCInstPredicate. An MCOpcodeSwitchStatement is a switch statement where the condition is a check on the machine opcode. It allows the definition of multiple checks, as well as a default case. More details on the grammar implemented by these two new constructs can be found in the diff for TargetInstrPredicates.td. This patch makes it easier to read the body of auto-generated TargetInstrInfo predicates. In future, I plan to reuse/extend the MCStatement grammar to describe more complex target hooks. For now, this is just a first step (mostly a minor cosmetic change to polish the new predicates framework). Differential Revision: https://reviews.llvm.org/D50457 llvm-svn: 339352
* [MC] Remove PhysRegSize from MCRegisterClassBjorn Pettersson2018-08-091-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: The interface to get size and spill size of a register was moved from MCRegisterInfo to TargetRegisterInfo over a year ago. Afaik the old interface has bee around to give out-of-tree targets a chance to adapt to the new interface. One problem with the old MCRegisterClass::PhysRegSize was that it represented the size of a register as "size in bits" / 8. So a register had to be a multiple of eight bits wide for the size to be correct (and the byte size for the target needed to be eight bits). Reviewers: kparzysz, qcolombet Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47199 llvm-svn: 339350
* [tablegen] Improve performance of -gen-register-info by replacing ↵Daniel Sanders2018-08-081-11/+51
| | | | | | | | | | | | | | | | | | | | | | | | barely-necessary std::map with a sorted vector Summary: This particular map is hardly ever queried and has a phased usage pattern (insert, iterate, query, insert, iterate) so it's a good candidate for a sorted vector and std::lower_bound. This significantly reduces the run time of runTargetDesc() in some circumstances. One llvm-tblgen invocation in my build improves the time spent in runTargetDesc() from 9.86s down to 0.80s (~92%) without changing the output. The same invocation also has 2GB less allocation churn. Reviewers: bogner, rtereshin, aditya_nandakumar, volkan Reviewed By: rtereshin Subscribers: mgrang, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D50272 llvm-svn: 339208
* Fix build bot after r338521Ulrich Weigand2018-08-011-1/+1
| | | | llvm-svn: 338522
* [SystemZ, TableGen] Fix shift count handlingUlrich Weigand2018-08-011-24/+20
| | | | | | | | | | | | | | | | | | | | | | | | | The DAG combiner logic to simplify AND masks in shift counts is invalid. While it is true that the SystemZ shift instructions ignore all but the low 6 bits of the shift count, it is still invalid to simplify the AND masks while the DAG still uses the standard shift operators (which are *not* defined to match the SystemZ instruction behavior). Instead, this patch performs equivalent operations during instruction selection. For completely removing the AND, this now happens via additional DAG match patterns implemented by a multi-alternative PatFrags. For simplifying a 32-bit AND to a 16-bit AND, the existing DAG patterns were already mostly OK, they just needed an output XForm to actually truncate the immediate value. Unfortunately, the latter change also exposed a bug in TableGen: it seems XForms are currently only handled correctly for direct operands of the outermost operation node. This patch also fixes that bug by simply recurring through the whole pattern. This should be NFC for all other targets. Differential Revision: https://reviews.llvm.org/D50096 llvm-svn: 338521
* Revert r338365: [X86] Improved sched models for X86 BT*rr instructions.Simon Pilgrim2018-07-312-94/+0
| | | | | | | | https://reviews.llvm.org/D49243 Contains WIP code that should not have been included. llvm-svn: 338369
* [X86] Improved sched models for X86 BT*rr instructions.Andrew V. Tischenko2018-07-312-0/+94
| | | | | | https://reviews.llvm.org/D49243 llvm-svn: 338365
* [windows] Don't inline fieldFromInstruction on WindowsStella Stamenova2018-07-251-1/+7
| | | | | | | | | | | | | | | Summary: The VS compiler (on Windows) has a bug which results in fieldFromInstruction being optimized out in some circumstances. This only happens in *release no debug info* builds that have assertions *turned off* - in all other situations the function is not inlined, so the functionality is correct. All of the bots have assertions turned on, so this path is not regularly tested. The workaround is to not inline the function on Windows - if the bug is fixed in a later release of the VS compiler, the noinline specification can be removed. The test that consistently reproduces this is Lanai v11.txt test. Reviewers: asmith, labath, zturner Subscribers: dblaikie, stella.stamenova, aprantl, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D49753 llvm-svn: 337942
* [Tablegen][PredicateExpander] Add the ability to define checks for invalid ↵Andrea Di Biagio2018-07-182-0/+10
| | | | | | | | registers. This was discussed in review D49436. llvm-svn: 337378
* [Tablegen][PredicateExpander] Fix a bug in `expandCheckImmOperand`.Andrea Di Biagio2018-07-171-4/+4
| | | | | | | | | | Function `expandCheckImmOperand` should always check if the input machine instruction is passed by reference before calling method `getOperand()` on it. Found while working on a patch that relies on `expandCheckImmOperand` to expand a scheduling predicate. llvm-svn: 337294
* [TableGen] std::move vectors into TreePatternNode.Craig Topper2018-07-152-10/+12
| | | | llvm-svn: 337121
* [TableGen] Remove what seems to be an unnecessary std::map copy.Craig Topper2018-07-151-9/+6
| | | | | | The comment says the copy was made so it could be destroyed in the following loop, but the original map wasn't used after the loop. llvm-svn: 337120
* [TableGen] Add some std::move to the PatternToMatch constructor.Craig Topper2018-07-151-1/+1
| | | | | | The are two vectors passed by value to the constructor. We should be able to move them into the object. llvm-svn: 337114
* [TableGen] Suppress type validation when parsing pattern fragmentsUlrich Weigand2018-07-132-4/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently, any attempt to define a PatFrag involving any floating-point only (or vector only) node causes a hard assertion failure in TableGen if the current target does not have any floating-point (or vector) types. This is annoying if you want to provide convenience fragments in common code (e.g. include/llvm/Target/TargetSelectionDAG.td) that is parsed on all platforms, including those that miss such types. But really, there's no reason not accept this when parsing the fragment -- of course it would be an error for such a target to actually *use* such a fragment anywhere, but as long as it doesn't, I think TableGen shouldn't error out. The immediate cause of the assertion failure is the test inside the ValidateOnExit destructor. This patch simply disables that check while infering types during parsing of pattern fragments (only). Reviewed By: hfinkel, kparzysz Differential Revision: https://reviews.llvm.org/D48887 llvm-svn: 337023
* [Tablegen] Optimize isSubsetOf() in AsmMatcherEmitter.cpp. NFCMarcello Maggioni2018-07-131-2/+10
| | | | | | | | | | | | | isSubsetOf() could be very slow if the hierarchy of the RegisterClasses of the target is very complicated. This is mainly caused by the fact that isSubset() is called multiple times over the same SuperClass of a register class if this ends up being the super class of a register class from multiple paths. Differential Revision: https://reviews.llvm.org/D49124 llvm-svn: 337020
* [cfi-verify] Support AArch64.Joel Galenson2018-07-134-0/+4
| | | | | | | | | | | | This patch adds support for AArch64 to cfi-verify. This required three changes to cfi-verify. First, it generalizes checking if an instruction is a trap by adding a new isTrap flag to TableGen (and defining it for x86 and AArch64). Second, the code that ensures that the operand register is not clobbered between the CFI check and the indirect call needs to allow a single dereference (in x86 this happens as part of the jump instruction). Third, we needed to ensure that return instructions are not counted as indirect branches. Technically, returns are indirect branches and can be covered by CFI, but LLVM's forward-edge CFI does not protect them, and x86 does not consider them, so we keep that behavior. In addition, we had to improve AArch64's code to evaluate the branch target of a MCInst to handle calls where the destination is not the first operand (which it often is not). Differential Revision: https://reviews.llvm.org/D48836 llvm-svn: 337007
* [TableGen] Support multi-alternative pattern fragmentsUlrich Weigand2018-07-136-375/+391
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A TableGen instruction record usually contains a DAG pattern that will describe the SelectionDAG operation that can be implemented by this instruction. However, there will be cases where several different DAG patterns can all be implemented by the same instruction. The way to represent this today is to write additional patterns in the Pattern (or usually Pat) class that map those extra DAG patterns to the instruction. This usually also works fine. However, I've noticed cases where the current setup seems to require quite a bit of extra (and duplicated) text in the target .td files. For example, in the SystemZ back-end, there are quite a number of instructions that can implement an "add-with-overflow" operation. The same instructions also need to be used to implement just plain addition (simply ignoring the extra overflow output). The current solution requires creating extra Pat pattern for every instruction, duplicating the information about which particular add operands map best to which particular instruction. This patch enhances TableGen to support a new PatFrags class, which can be used to encapsulate multiple alternative patterns that may all match to the same instruction. It operates the same way as the existing PatFrag class, except that it accepts a list of DAG patterns to match instead of just a single one. As an example, we can now define a PatFrags to match either an "add-with-overflow" or a regular add operation: def z_sadd : PatFrags<(ops node:$src1, node:$src2), [(z_saddo node:$src1, node:$src2), (add node:$src1, node:$src2)]>; and then use this in the add instruction pattern: defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; These SystemZ target changes are implemented here as well. Note that PatFrag is now defined as a subclass of PatFrags, which means that some users of internals of PatFrag need to be updated. (E.g. instead of using PatFrag.Fragment you now need to use !head(PatFrag.Fragments).) The implementation is based on the following main ideas: - InlinePatternFragments may now replace each original pattern with several result patterns, not just one. - parseInstructionPattern delays calling InlinePatternFragments and InferAllTypes. Instead, it extracts a single DAG match pattern from the main instruction pattern. - Processing of the DAG match pattern part of the main instruction pattern now shares most code with processing match patterns from the Pattern class. - Direct use of main instruction patterns in InferFromPattern and EmitResultInstructionAsOperand is removed; everything now operates solely on DAG match patterns. Reviewed by: hfinkel Differential Revision: https://reviews.llvm.org/D48545 llvm-svn: 336999
* [TableGen] Add a general-purpose JSON backend.Simon Tatham2018-07-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The aim of this backend is to output everything TableGen knows about the record set, similarly to the default -print-records backend. But where -print-records produces output in TableGen's input syntax (convenient for humans to read), this backend produces it as structured JSON data, which is convenient for loading into standard scripting languages such as Python, in order to extract information from the data set in an automated way. The output data contains a JSON representation of the variable definitions in output 'def' records, and a few pieces of metadata such as which of those definitions are tagged with the 'field' prefix and which defs are derived from which classes. It doesn't dump out absolutely every piece of knowledge it _could_ produce, such as type information and complicated arithmetic operator nodes in abstract superclasses; the main aim is to allow consumers of this JSON dump to essentially act as new backends, and backends don't generally need to depend on that kind of data. The new backend is implemented as an EmitJSON() function similar to all of llvm-tblgen's other EmitFoo functions, except that it lives in lib/TableGen instead of utils/TableGen on the basis that I'm expecting to add it to clang-tblgen too in a future patch. To test it, I've written a Python script that loads the JSON output and tests properties of it based on comments in the .td source - more or less like FileCheck, except that the CHECK: lines have Python expressions after them instead of textual pattern matches. Reviewers: nhaehnle Reviewed By: nhaehnle Subscribers: arichardson, labath, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D46054 llvm-svn: 336771
* [TableGen] Fix some bad formatting. NFCCraig Topper2018-07-111-4/+4
| | | | llvm-svn: 336751
* [Power9] Add __float128 builtins for Round To OddStefan Pintilie2018-07-091-1/+3
| | | | | | | | | | | | GCC has builtins for these round to odd instructions: __float128 __builtin_sqrtf128_round_to_odd (__float128) __float128 __builtin_{add,sub,mul,div}f128_round_to_odd (__float128, __float128) __float128 __builtin_fmaf128_round_to_odd (__float128, __float128, __float128) Differential Revision: https://reviews.llvm.org/D47550 llvm-svn: 336578
* [TableGen] Increase the number of supported decoder fix-ups.Sander de Smalen2018-07-051-18/+40
| | | | | | | | | | | | | | | | The vast number of added instructions for SVE causes TableGen to fail with an assertion: Assertion `Delta < 65536U && "disassembler decoding table too large!"' This patch increases the number of supported decoder fix-ups. Reviewers: dmgreen, stoklund, petpav01 Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D48937 llvm-svn: 336334
* [X86] Add phony registers for high halves of regs with low halvesKrzysztof Parzyszek2018-07-021-3/+9
| | | | | | | | | | Add registers still missing after r328016 (D43353): - for bits 15-8 of SI, DI, BP, SP (*H), and R8-R15 (*BH), - for bits 31-16 of R8-R15 (*WH). Thanks to Craig Topper for pointing it out. llvm-svn: 336134
* [NFC] Prefer (void) to LLVM_ATTRIBUTE_UNUSED for unused var in ↵Andrei Elovikov2018-06-261-2/+2
| | | | | | | | | | | | | | GlobalISElemitter.cpp. Reviewers: dsanders, craig.topper Reviewed By: dsanders Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48534 llvm-svn: 335581
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