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* Add asserts to ensure that values will fit into the tables.Craig Topper2012-03-061-1/+16
| | | | llvm-svn: 152104
* Nuke a bit of dead code.Jim Grosbach2012-03-051-2/+0
| | | | llvm-svn: 152067
* ARM Refactor VLD/VST spaced pair instructions.Jim Grosbach2012-03-051-2/+1
| | | | | | Use the new composite physical registers. llvm-svn: 152063
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-051-0/+1
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. llvm-svn: 152045
* Shrink and reorder fields in MCRegisterClass to reduce size of static data.Craig Topper2012-03-051-5/+5
| | | | llvm-svn: 152019
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-7/+7
| | | | | | static data size. llvm-svn: 152016
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-2/+2
| | | | llvm-svn: 152001
* Use uint16_t instead of unsigned to store registers in reg classes. Reduces ↵Craig Topper2012-03-041-11/+11
| | | | | | static data size. llvm-svn: 151998
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-041-2/+2
| | | | | | size of static data. llvm-svn: 151996
* Use uint8_t instead of enums to store values in X86 disassembler table. ↵Craig Topper2012-03-041-8/+8
| | | | | | Shaves 150k off the size of X86DisassemblerDecoder.o llvm-svn: 151995
* Perform the string table optimization for OperandMatchEntries too.Benjamin Kramer2012-03-031-10/+28
| | | | llvm-svn: 151986
* Shrink the asm matcher tables.Benjamin Kramer2012-03-031-8/+23
| | | | | | | | | | | | - Shrink the opcode field to 16 bits. - Shrink the AsmVariantID field to 8 bits. - Store the mnemonic string in a string table, store a 16 bit index. - Store a pascal-style length byte in the string instead of a null terminator, so we can avoid calling strlen on every entry we visit during mnemonic search. Shrinks X86AsmParser.o from 434k to 201k on x86_64 and eliminates relocs from the table. llvm-svn: 151984
* StringToOffsetTable: Allow uniquing the first element, add an option to skip ↵Benjamin Kramer2012-03-031-6/+7
| | | | | | appending a terminating null. llvm-svn: 151983
* Move getSubRegIndex out of generated code into MCRegisterInfo, devirtualize it.Benjamin Kramer2012-03-011-11/+0
| | | | llvm-svn: 151821
* Move TargetRegisterInfo::getSubReg() to MCRegisterInfo.Jim Grosbach2012-03-011-51/+56
| | | | | | | | Allows us to de-virtualize the function and provides access to it in the instruction printer, which is useful for handling composite physical registers (e.g., ARM register lists). llvm-svn: 151815
* Revert "Emit the SubRegTable with the smallest possible integer type."Jim Grosbach2012-03-014-14/+11
| | | | | | | | | | This reverts commit 151760. We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo, but to do that, the type of the lookup table needs to be the same for all targets. llvm-svn: 151814
* Make TargetRegisterClasses non-virtual by making the only virtual function a ↵Benjamin Kramer2012-03-011-44/+41
| | | | | | | | | | | function pointer. This allows us to make TRC non-polymorphic and value-initializable, eliminating a huge static initializer and a ton of cruft from the generated code. Shrinks ARMBaseRegisterInfo.o by ~100k. llvm-svn: 151806
* Emit the "is an intrinsic overloaded" table as a bitfield.Benjamin Kramer2012-03-011-7/+10
| | | | llvm-svn: 151792
* Emit the intrinsic modref info as a lookup table instead of a huge switch.Benjamin Kramer2012-03-011-16/+18
| | | | | | Shrinks BasicAliasAnalysis.o from 106k to 56k on i386. llvm-svn: 151781
* Implement getSubRegIndex as a linear search on the SubRegTable instead of ↵Benjamin Kramer2012-02-291-14/+6
| | | | | | | | | using a big switch. - The search bounds are constant, in the worst case (ARM target) it will scan over 30 uint16_ts. - This method isn't very hot, I had problems finding a testcase where it's called more than a dozen of times (no perf impact). llvm-svn: 151773
* Tidy up. 80 columns.Jim Grosbach2012-02-292-14/+23
| | | | llvm-svn: 151764
* Emit the SubRegTable with the smallest possible integer type.Benjamin Kramer2012-02-294-11/+14
| | | | | | Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets. llvm-svn: 151760
* Tidy up. Spelling.Jim Grosbach2012-02-291-2/+2
| | | | llvm-svn: 151758
* Move the subregister indicies enum into the REGINFO_ENUM section.Jim Grosbach2012-02-291-15/+14
| | | | llvm-svn: 151756
* Switch TargetRegisterInfo::getSubReg() to use a lookup table.Jim Grosbach2012-02-291-18/+34
| | | | | | | | Instead of nested switch statements, use a lookup table. On ARM, this replaces a 23k (x86_64 release build) function with a 16k table. Its not unlikely to be faster, as well. llvm-svn: 151751
* Convert generated intrinsic attributes to use an array lookup as Chris ↵Craig Topper2012-02-281-18/+26
| | | | | | suggested in PR11951. llvm-svn: 151622
* Update tblgen command guide. Remove unused tblgen InstrEnumEmitter files.Craig Topper2012-02-273-82/+0
| | | | llvm-svn: 151513
* X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper2012-02-273-0/+16
| | | | | | Kay Tiong Khoo. llvm-svn: 151510
* Remove 'if' from getSuperRegisters, getSubRegisters, and getOverlaps that ↵Craig Topper2012-02-231-1/+1
| | | | | | were added in r151038. llvm-svn: 151246
* Declare register classes as const. Fix a couple pointers to register classes ↵Craig Topper2012-02-221-3/+4
| | | | | | that weren't already const. llvm-svn: 151138
* Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper2012-02-221-2/+2
| | | | | | to static data that should not be modified. llvm-svn: 151134
* Reorder some members in MCRegisterClass to remove padding on 64-bit builds.Craig Topper2012-02-211-2/+2
| | | | llvm-svn: 151043
* In generated RegisterInfo files, replace a pointer to the end of an array ↵Craig Topper2012-02-211-4/+2
| | | | | | with just the size of the array to avoid relocations. llvm-svn: 151041
* Merge some tables in generated RegisterInfo file. Store indices into larger ↵Craig Topper2012-02-211-28/+48
| | | | | | table instead of pointers to reduce relocations and shrink table size on 64-bit builds. Shaves ~24K off X86MCTargetDesc.o. Accidentally commited only part of this in r151038. llvm-svn: 151039
* Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles2012-02-191-2/+0
| | | | llvm-svn: 150918
* Add vmfunc instruction to X86 assembler and disassembler.Craig Topper2012-02-191-8/+9
| | | | llvm-svn: 150899
* Add X86 assembler and disassembler support for AMD SVM instructions. ↵Craig Topper2012-02-182-1/+11
| | | | | | Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. llvm-svn: 150873
* Make the EDis tables const.Benjamin Kramer2012-02-111-5/+1
| | | | llvm-svn: 150304
* Reuse the enum names from X86Desc in the X86Disassembler.Benjamin Kramer2012-02-111-1/+1
| | | | | | | This requires some gymnastics to make it available for C code. Remove the names from the disassembler tables, making them relocation free. llvm-svn: 150303
* Put instruction names into an indexed string table on the side, removing a ↵Benjamin Kramer2012-02-101-2/+20
| | | | | | | | | pointer from MCInstrDesc. Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64. llvm-svn: 150245
* Store just the SimpleValueType in the generated VT tables for each register ↵Benjamin Kramer2012-02-091-1/+1
| | | | | | class, eliminating static ctors. llvm-svn: 150173
* Move the Name field in MCInstrDesc to the end, saving 8 bytes of padding per ↵Benjamin Kramer2012-02-091-2/+3
| | | | | | | | entry on x86_64. No change on i386. llvm-svn: 150170
* Teach the MC and disassembler about SoftFail, and hook it up to ↵James Molloy2012-02-091-2/+76
| | | | | | UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage. llvm-svn: 150169
* More tweaks to get the size of the X86 disassembler tables down.Craig Topper2012-02-091-7/+28
| | | | llvm-svn: 150167
* Flatten some of the arrays in the X86 disassembler tables to reduce space ↵Craig Topper2012-02-091-38/+38
| | | | | | needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953. llvm-svn: 150161
* Don't map registers to the invalid dwarf register (-1). It's the default value.Benjamin Kramer2012-02-081-0/+3
| | | | | | | X86GenRegisterInfo.inc | 1032 ------------------------------------------------- 1 file changed, 1032 deletions(-) llvm-svn: 150080
* Value initialize MCRegisterClasses. Not sure how could miss this during the ↵Benjamin Kramer2012-02-081-2/+2
| | | | | | MCTargetDesc refactor. llvm-svn: 150076
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-0511-41/+33
| | | | llvm-svn: 149814
* Increment DFAStateEntryTable index for sentinel entry.Brendon Cahoon2012-02-031-1/+3
| | | | | | | | | When adding the {-1, -1} entry to the DFAStateInputTable, we need to increment the index used to populate the DFAStateEntryTable. Otherwise, the entry table will be off by one for each transition after the {-1, -1} entry. PR11908. llvm-svn: 149713
* Specify SubRegIndex components on the index itself.Jakob Stoklund Olesen2012-02-012-25/+77
| | | | | | | | | | | | | | | | | It is simpler to define a composite index directly: def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>; def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>; Than specifying the composite indices on each register: CompositeIndices = [(ssub_2 dsub_1, ssub_0), (ssub_3 dsub_1, ssub_1)] in ... This also makes it clear that SubRegIndex composition is supposed to be unique. llvm-svn: 149556
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