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* Fix a bug in the TopoOrderRC comparison function.Jakob Stoklund Olesen2012-02-011-1/+1
| | | | | | | | | | | The final tie breaker comparison also needs to return +/-1, or 0. This is not a less() function. This could cause otherwise identical super-classes to be ordered unstably, depending on what the system qsort routine does with a bad compare function. llvm-svn: 149549
* Avoid emitting empty arrays, they're not standard C++.Jakob Stoklund Olesen2012-02-011-6/+11
| | | | | | | It's only by luck that we haven't produced any yet, and clang refuses to compile them. llvm-svn: 149546
* Don't assign a value to NUM_TARGET_NAMED_SUBREGS.Jakob Stoklund Olesen2012-01-311-2/+1
| | | | | | It was wrong and completely unused. llvm-svn: 149433
* Move the composite map into CodeGenSubRegIndex.Jakob Stoklund Olesen2012-01-313-30/+51
| | | | | | Each SubRegIndex keeps track of how it composes. llvm-svn: 149423
* Add a TableGen CodeGenSubRegIndex class.Jakob Stoklund Olesen2012-01-313-64/+144
| | | | | | | | | This class is used to represent SubRegIndex instances instead of the raw Record pointers that were used before. No functional change intended. llvm-svn: 149418
* Tidy up. Trailing whitespace.Jim Grosbach2012-01-241-24/+24
| | | | llvm-svn: 148856
* Widen the instruction encoder that TblGen emits to a 64 bits, which should ↵Owen Anderson2012-01-241-7/+7
| | | | | | accomodate every target I can think of offhand. llvm-svn: 148833
* Add an (interleave A, B, ...) SetTheory operator.Jakob Stoklund Olesen2012-01-241-0/+19
| | | | | | This will interleave the elements from two or more lists. llvm-svn: 148824
* Add a CoveredBySubRegs property to Register descriptions.Jakob Stoklund Olesen2012-01-182-12/+41
| | | | | | | | | | | | | | | | When set, this bit indicates that a register is completely defined by the value of its sub-registers. Use the CoveredBySubRegs property to infer which super-registers are call-preserved given a list of callee-saved registers. For example, the ARM registers D8-D15 are callee-saved. This now automatically implies that Q4-Q7 are call-preserved. Conversely, Win64 callees save XMM6-XMM15, but the corresponding YMM6-YMM15 registers are not call-preserved because they are not fully defined by their sub-registers. llvm-svn: 148363
* Add TableGen support for callee saved registers.Jakob Stoklund Olesen2012-01-173-0/+56
| | | | | | | | | Targets can now add CalleeSavedRegs defs to their *CallingConv.td file. TableGen will use this to create a *_SaveList array suitable for returning from getCalleeSavedRegs() as well as a *_RegMask bit mask suitable for returning from getCallPreservedMask(). llvm-svn: 148346
* Intel syntax: Ignore mnemonic aliases.Devang Patel2012-01-171-1/+3
| | | | llvm-svn: 148316
* Provide better messages in llvm_unreachable.David Blaikie2012-01-171-1/+1
| | | | llvm-svn: 148293
* Remove unreachable code. (replace with llvm_unreachable to help GCC where ↵David Blaikie2012-01-172-2/+2
| | | | | | necessary) llvm-svn: 148284
* Removing unused default switch cases in switches over enums that already ↵David Blaikie2012-01-161-3/+0
| | | | | | | | account for all enumeration values explicitly. (This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them) llvm-svn: 148262
* Skip the NAME field when forming tuples.Jakob Stoklund Olesen2012-01-131-0/+3
| | | | llvm-svn: 148147
* Delete CodeInit and CodeRecTy from TableGen.Jakob Stoklund Olesen2012-01-132-4/+4
| | | | | | | The code type was always identical to a string anyway. Now it is simply a synonym. The code literal syntax [{...}] is still valid. llvm-svn: 148092
* Added MVT::v2f16Pete Cooper2012-01-121-0/+1
| | | | llvm-svn: 148067
* Record asm variant id in MatchEntry and check it while matching instruction.Devang Patel2012-01-101-6/+14
| | | | llvm-svn: 147858
* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-104-5/+0
| | | | llvm-svn: 147855
* Use descriptive variable name and remove incorrect operand number check.Devang Patel2012-01-091-12/+9
| | | | llvm-svn: 147802
* Split AsmParser into two components - AsmParser and AsmParserVariantDevang Patel2012-01-093-77/+111
| | | | | | | AsmParser holds info specific to target parser. AsmParserVariant holds info specific to asm variants supported by the target. llvm-svn: 147787
* Remove VectorExtras. This unused helper was written for a type of API that ↵Benjamin Kramer2012-01-071-1/+0
| | | | | | is discouraged now. llvm-svn: 147738
* Fix TableGen so that it will emit the correct signature for FastEmit_f:Cameron Zwarich2012-01-071-1/+1
| | | | | | | | | | | | | | | | | /// FastEmit_f - This method is called by target-independent code /// to request that an instruction with the given type, opcode, and /// floating-point immediate operand be emitted. virtual unsigned FastEmit_f(MVT VT, MVT RetVT, unsigned Opcode, const ConstantFP *FPImm); Currently, it emits an accidentally overloaded version without the const on the ConstantFP*. This doesn't affect anything in the tree, since nothing causes that method to be autogenerated, but I have been playing with some ARM TableGen refactorings that hit this problem. llvm-svn: 147727
* Refactor.Devang Patel2012-01-071-38/+45
| | | | | | Store AsmParser info locally. A small step towards emitting match entries for multiple asm variants. llvm-svn: 147710
* Eliminate an error check that may not work with all asm syntax variants.Devang Patel2012-01-071-1/+2
| | | | llvm-svn: 147708
* Do not hard code asm variant number.Devang Patel2012-01-051-2/+7
| | | | llvm-svn: 147583
* Don't use enums larger than 1 << 31 for target features.Jakob Stoklund Olesen2012-01-031-16/+29
| | | | | | Patch by Andy Zhang! llvm-svn: 147491
* Add disassembler support for VPERMIL2PD and VPERMIL2PS.Craig Topper2011-12-301-5/+9
| | | | llvm-svn: 147368
* Add FMA4 instructions to disassembler.Craig Topper2011-12-302-1/+10
| | | | llvm-svn: 147367
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-221-0/+2
| | | | | | rdar://10558523 llvm-svn: 147189
* ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.Jim Grosbach2011-12-211-0/+1
| | | | llvm-svn: 147025
* Fix up the CMake build for the new files added in r146960, they'reChandler Carruth2011-12-201-0/+1
| | | | | | likely to stay either way that discussion ends up resolving itself. llvm-svn: 146966
* Revert pragma clang suppressions that confuse GCC. (I'll worry about how to ↵David Blaikie2011-12-201-5/+0
| | | | | | suppress/fix these problems properly when we figure out how to keep LLVM -Wweak-vtables clean) llvm-svn: 146965
* Unweaken vtables as per ↵David Blaikie2011-12-208-93/+142
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Add basic generic CodeGen support for half.Dan Gohman2011-12-202-0/+3
| | | | llvm-svn: 146927
* Emit a getMatchingSuperRegClass() implementation for every target.Jakob Stoklund Olesen2011-12-193-2/+80
| | | | | | | | | Use information computed while inferring new register classes to emit accurate, table-driven implementations of getMatchingSuperRegClass(). Delete the old manual, error-prone implementations in the targets. llvm-svn: 146873
* Synthesize register classes for TRI::getMatchingSuperRegClass().Jakob Stoklund Olesen2011-12-192-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Teach TableGen to create the missing register classes needed for getMatchingSuperRegClass() to return maximal results. The function is still not auto-generated, so it still returns inexact results. This produces these new register classes: ARM: QQPR_with_dsub_0_in_DPR_8 QQQQPR_with_dsub_0_in_DPR_8 X86: GR64_with_sub_32bit_in_GR32_NOAX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP GR64_with_sub_16bit_in_GR16_NOREX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX GR64_with_sub_32bit_in_GR32_TC GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC GR64_with_sub_32bit_in_GR32_AD GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX The other targets in the tree are not weird enough to be affected. llvm-svn: 146872
* Extract a method. No functional change.Jakob Stoklund Olesen2011-12-162-36/+47
| | | | llvm-svn: 146713
* Use the proper comparator for set_intersection.Jakob Stoklund Olesen2011-12-151-1/+2
| | | | llvm-svn: 146674
* Synthesize missing register class intersections.Jakob Stoklund Olesen2011-12-152-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function TRI::getCommonSubClass(A, B) returns the largest common sub-class of the register classes A and B. This patch teaches TableGen to synthesize sub-classes such that the answer is always maximal. In other words, every register that is in both A and B will also be present in getCommonSubClass(A, B). This introduces these synthetic register classes: ARM: GPRnopc_and_hGPR GPRnopc_and_hGPR hGPR_and_rGPR GPRnopc_and_hGPR GPRnopc_and_hGPR hGPR_and_rGPR tGPR_and_tcGPR hGPR_and_tcGPR X86: GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR64_NOSP_and_GR64_TC GR64_NOSP_and_GR64_TC GR64_NOREX_and_GR64_TC GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR64_NOSP_and_GR64_TC GR64_NOREX_and_GR64_TC GR64_NOREX_NOSP_and_GR64_TC GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR32_ABCD_and_GR32_NOAX GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR32_ABCD_and_GR32_NOAX GR32_NOAX_and_GR32_TC GR32_NOAX_and_GR32_NOSP GR64_NOSP_and_GR64_TC GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR64_NOREX_and_GR64_TC GR64_NOREX_NOSP_and_GR64_TC GR32_ABCD_and_GR32_NOAX GR64_ABCD_and_GR64_TC GR32_NOAX_and_GR32_TC GR32_AD_and_GR32_NOAX Other targets are unaffected. llvm-svn: 146657
* LLVMBuild: Remove trailing newline, which irked me.Daniel Dunbar2011-12-121-1/+0
| | | | llvm-svn: 146409
* Extract a method.Jakob Stoklund Olesen2011-12-122-14/+26
| | | | llvm-svn: 146374
* ARM: NEON SHLL instruction immediate operand range checking.Jim Grosbach2011-12-071-0/+6
| | | | llvm-svn: 146003
* Extend AsmMatcher token literal matching to allow aliasing.Jim Grosbach2011-12-061-27/+32
| | | | | | | | | | | | | | | | | For example, ARM allows: vmov.u32 s4, #0 -> vmov.i32, #0 'u32' is a more specific designator for the 32-bit integer type specifier and is legal for any instruction which accepts 'i32' as a datatype suffix. We want to say, def : TokenAlias<".u32", ".i32">; This works by marking the match class of 'From' as a subclass of the match class of 'To'. rdar://10435076 llvm-svn: 145992
* First chunk of MachineInstr bundle support.Evan Cheng2011-12-061-0/+1
| | | | | | | | | 1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs llvm-svn: 145975
* Tidy up. Fix naming convention stuff for some internal functions.Jim Grosbach2011-12-061-12/+12
| | | | llvm-svn: 145974
* use space star instead of star spaceSebastian Pop2011-12-063-29/+29
| | | | llvm-svn: 145944
* add missing point at the end of sentencesSebastian Pop2011-12-062-66/+66
| | | | llvm-svn: 145943
* ARM NEON VEXT aliases for data type suffices.Jim Grosbach2011-12-021-0/+2
| | | | llvm-svn: 145726
* TableGen: fix CMake build s'moreDylan Noblesmith2011-12-011-0/+1
| | | | | | Oops, missed another missing file from r145629. llvm-svn: 145636
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