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* Fix a warning from gcc-4.0 (from the ppc buildbot).Bob Wilson2010-07-281-0/+2
| | | | llvm-svn: 109605
* Filter out patterns that have PredicateOperands.Eric Christopher2010-07-281-0/+12
| | | | llvm-svn: 109572
* Return -1 only on failure to execute a program.Mikhail Glushenkov2010-07-271-1/+1
| | | | | | Also fix some comments. llvm-svn: 109499
* 80-col.Eric Christopher2010-07-261-2/+4
| | | | llvm-svn: 109407
* Get rid of exceptions in llvmc.Mikhail Glushenkov2010-07-231-35/+51
| | | | | | llvmc can be now compiled with llvm-gcc on Windows. llvm-svn: 109215
* Hack around extracts that aren't easy to process.Eric Christopher2010-07-211-0/+4
| | | | llvm-svn: 109043
* remove option from tablegen for building static header.Chris Lattner2010-07-203-27/+1
| | | | llvm-svn: 108893
* Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!Bruno Cardoso Lopes2010-07-191-0/+1
| | | | llvm-svn: 108769
* Remove code duplication.Mikhail Glushenkov2010-07-191-26/+21
| | | | llvm-svn: 108718
* Better error reporting for switch_list.Mikhail Glushenkov2010-07-191-9/+42
| | | | llvm-svn: 108714
* TblGen/AsmMatcher: Add support for honoring instruction Requires<[]> ↵Daniel Dunbar2010-07-191-2/+136
| | | | | | | | attributes as part of the matcher. - Currently includes a hack to limit ourselves to "In32BitMode" and "In64BitMode", because we don't have the other infrastructure to properly deal with setting SSE, etc. features on X86. llvm-svn: 108677
* llvmc: Add a new option type (switch_list).Mikhail Glushenkov2010-07-191-8/+43
| | | | llvm-svn: 108673
* Update comment.Bill Wendling2010-07-161-1/+1
| | | | llvm-svn: 108571
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-161-1/+1
| | | | | | thus is a much more meaningful name. llvm-svn: 108563
* Convert some tab stops into spaces.Duncan Sands2010-07-123-4/+4
| | | | llvm-svn: 108130
* Replace copyRegToReg with COPY in FastISelEmitter.Jakob Stoklund Olesen2010-07-111-13/+9
| | | | llvm-svn: 108071
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-101-2/+2
| | | | | | | | | - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
* Start the support for AVX instructions with 256-bit %ymm registers. A couple ofBruno Cardoso Lopes2010-07-091-0/+2
| | | | | | | | | | | | | | | notes: - The instructions are being added with dummy placeholder patterns using some 256 specifiers, this is not meant to work now, but since there are some multiclasses generic enough to accept them, when we go for codegen, the stuff will be already there. - Add VEX encoding bits to support YMM - Add MOVUPS and MOVAPS in the first round - Use "Y" as suffix for those Instructions: MOVUPSYrr, ... - All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX file. llvm-svn: 107996
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h llvm-svn: 107987
* These changes should have accompanied r107943.Dan Gohman2010-07-091-2/+2
| | | | llvm-svn: 107947
* Changes to ARM tail calls, mostly cosmetic.Dale Johannesen2010-07-081-2/+2
| | | | | | | | | Add explicit testcases for tail calls within the same module. Duplicate some code to humor those who think .w doesn't apply on ARM. Leave this disabled on Thumb1, and add some comments explaining why it's hard and won't gain much. llvm-svn: 107851
* Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman2010-07-081-2/+2
| | | | | | Debug info intrinsics win for now. llvm-svn: 107850
* Implement the major chunk of PR7195: support for 'callw'Chris Lattner2010-07-072-0/+3
| | | | | | | in the integrated assembler. Still some discussion to be done. llvm-svn: 107825
* Give FunctionLoweringInfo an MBB member, avoiding the need to pass itDan Gohman2010-07-071-2/+2
| | | | | | | | around everywhere, and also give it an InsertPt member, to enable isel to operate at an arbitrary position within a block, rather than just appending to a block. llvm-svn: 107791
* Add a new target independent COPY instruction and code to lower it.Jakob Stoklund Olesen2010-07-021-0/+1
| | | | | | | | | | | The COPY instruction is intended to replace the target specific copy instructions for virtual registers as well as the EXTRACT_SUBREG and INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection DAG. COPY is lowered to native register copies by LowerSubregs. llvm-svn: 107529
* Clean up TargetOpcodes.h a bit, and limit the number of places where the fullJakob Stoklund Olesen2010-07-022-88/+33
| | | | | | | | | list of predefined instructions appear. Add some consistency checks. Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it is hardly worth the effort. llvm-svn: 107520
* Remove unused variables.Duncan Sands2010-06-251-1/+0
| | | | llvm-svn: 106834
* Change array references to match my previous change to use the public typeBob Wilson2010-06-241-1/+1
| | | | | | names for the array fields. llvm-svn: 106803
* Fix up some comments.Bob Wilson2010-06-241-4/+4
| | | | llvm-svn: 106795
* Use the struct tags mandated by ARM's ABI. Also use the public type names forBob Wilson2010-06-241-4/+51
| | | | | | the array fields in these structs. llvm-svn: 106794
* Add support for the x86 instructions "pusha" and "popa".Nico Weber2010-06-231-0/+4
| | | | llvm-svn: 106671
* Fix a tblgen bug.Bruno Cardoso Lopes2010-06-231-1/+1
| | | | | | | | | | | | | | | | | Given the pattern below as an example: list<dag> Pattern = [(set RC:$dst, (v4f32 (shufp:src3 RC:$src1, (mem_frag addr:$src2))))]; The right reference resolving should lead to: list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp:src3 VR128:$src1, (mem_frag addr:$src2))))]; But was yielding: list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp VR128:$src1, (mem_frag addr:$src2))))]; Fix this by passing the right name when creating a new DagInit node. llvm-svn: 106670
* Don't link against libm and libpthread which don't exist in BeOS/Haiku. Also,Nick Lewycky2010-06-231-1/+1
| | | | | | Haiku like Linux provides <regex.h>, so use it. Patch by Paul Davey! llvm-svn: 106620
* Fix a subtle multiclass bug: when using class inheritance onBruno Cardoso Lopes2010-06-221-4/+4
| | | | | | a toplevel 'defm', make sure to properly resolve references. llvm-svn: 106570
* Remove isTwoAddress from llvm.Eric Christopher2010-06-211-11/+0
| | | | llvm-svn: 106470
* Add support for returning multiple vectors via sret, which is how the ARM ↵Nate Begeman2010-06-201-30/+42
| | | | | | target expects the intrinsics to work. llvm-svn: 106406
* An attempt to fix the problem Anton reported withDale Johannesen2010-06-181-0/+1
| | | | | | | ARM tail calls. Don't know if it works, but it doesn't break Darwin. llvm-svn: 106309
* Teach tablegen how to inherit from classes in 'defm' definitions.Bruno Cardoso Lopes2010-06-181-0/+50
| | | | | | | The rule is simple: only inherit from a class list if they come in the end, after the last multiclass. llvm-svn: 106305
* Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman2010-06-182-2/+3
| | | | | | | MachineRegisterInfo doesn't have to confusingly allocate an extra entry. llvm-svn: 106296
* In case Rec is a definition and not a class, do the proper comparison!Bruno Cardoso Lopes2010-06-171-1/+9
| | | | llvm-svn: 106246
* Modify tablegen to support generating all NEON code used by clang at once.Nate Begeman2010-06-172-89/+135
| | | | llvm-svn: 106207
* Fix the handling of !if result, avoiding null results for non 'int'.Bruno Cardoso Lopes2010-06-171-4/+6
| | | | llvm-svn: 106201
* For a tablegen expression such as !if(a,b,c), let 'a'Bruno Cardoso Lopes2010-06-171-2/+4
| | | | | | be evaluated for 'bit' operators llvm-svn: 106185
* Fix the typo in my previous one-line commit.Alexis Hunt2010-06-171-1/+1
| | | | llvm-svn: 106179
* Make sure CMake can build the files added by my previous commit.Alexis Hunt2010-06-161-0/+1
| | | | llvm-svn: 106178
* Add preliminary clang attribute generation support.Alexis Hunt2010-06-163-0/+147
| | | | | | | The attribute class generation support is still somewhat limited. See the accompanying clang commit for more details. llvm-svn: 106174
* let the '!eq' expression support 'int' and 'bit' typesBruno Cardoso Lopes2010-06-161-1/+12
| | | | llvm-svn: 106171
* Make VC++ happy Nate Begeman2010-06-151-11/+11
| | | | llvm-svn: 106054
* Next round of tail call changes. Register used in a tailDale Johannesen2010-06-152-1/+3
| | | | | | | | call must not be callee-saved; following x86, add a new regclass to represent this. Also fixes a couple of bugs. Still disabled by default; Thumb doesn't work yet. llvm-svn: 106053
* generate better code in CheckComplexPatternChris Lattner2010-06-141-2/+3
| | | | llvm-svn: 105970
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