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* Revert r178166. According to Howard, this code is actually ok.Dan Gohman2013-03-291-3/+1
| | | | llvm-svn: 178319
* Avoid undefined behavior from passing a std::vector's own contentsDan Gohman2013-03-271-1/+3
| | | | | | in as an argument to push_back. llvm-svn: 178166
* TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.Andrew Trick2013-03-262-2/+24
| | | | | | Allow variants to be defined only for some processors on a target. llvm-svn: 178074
* x86 -- add the XTEST instructionDave Zarzycki2013-03-251-8/+9
| | | | llvm-svn: 177888
* Allow types to be omitted in output patterns.Jakob Stoklund Olesen2013-03-242-0/+16
| | | | | | | | | | This syntax is now preferred: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; There is no reason to repeat the types in the output pattern. llvm-svn: 177844
* Allow direct value types to be used in instruction 'set' patterns.Jakob Stoklund Olesen2013-03-241-2/+24
| | | | | | | | | | | | This makes it possible to define instruction patterns like this: def LDri : F3_2<3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr), "ld [$addr], $dst", [(set i32:$dst, (load ADDRri:$addr))]>; ~~~ llvm-svn: 177834
* Allow direct value types in pattern definitions.Jakob Stoklund Olesen2013-03-232-5/+29
| | | | | | | | | | | | | | | | | Just like register classes, value types can be used in two ways in patterns: (sext_inreg i32:$src, i16) In a named leaf node like i32:$src, the value type simply provides the type of the node directly. This simplifies type inference a lot compared to the current practice of specifiying types indirectly with register classes. As an unnamed leaf node, like i16 above, the value type represents itself as an MVT::Other immediate. llvm-svn: 177828
* Make all unnamed RegisterClass TreePatternNodes typed MVT::i32.Jakob Stoklund Olesen2013-03-232-21/+21
| | | | | | | | | | | | | | | | | | | | | A register class can appear as a leaf TreePatternNode with and without a name: (COPY_TO_REGCLASS GPR:$src, F8RC) In a named leaf node like GPR:$src, the register class provides type information for the named variable represented by the node. The TypeSet for such a node is the set of value types that the register class can represent. In an unnamed leaf node like F8RC above, the register class represents itself as a kind of immediate. Such a node has the type MVT::i32, we'll never create a virtual register representing it. This change makes it possible to remove the special handling of COPY_TO_REGCLASS in CodeGenDAGPatterns.cpp. llvm-svn: 177825
* Add TableGen ctags(1) emitter and helper script.Sean Silva2013-03-215-1/+561
| | | | | | | | | | | | | | | | | | | | | To use this in conjunction with exuberant ctags to generate a single combined tags file, run tblgen first and then $ ctags --append [...] Since some identifiers have corresponding definitions in C++ code, it can be useful (if using vim) to also use cscope, and :set cscopetagorder=1 so that :tag X will preferentially select the tablegen symbol, while :cscope find g X will always find the C++ symbol. Patch by Kevin Schoedel! (a couple small formatting changes courtesy of clang-format) llvm-svn: 177682
* Extend TableGen instruction selection matcher to improve handlingUlrich Weigand2013-03-192-11/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of complex instruction operands (e.g. address modes). Currently, if a Pat pattern creates an instruction that has a complex operand (i.e. one that consists of multiple sub-operands at the MI level), this operand must match a ComplexPattern DAG pattern with the correct number of output operands. This commit extends TableGen to alternatively allow match a complex operands against multiple separate operands at the DAG level. This allows using Pat patterns to match pre-increment nodes like pre_store (which must have separate operands at the DAG level) onto an instruction pattern that uses a multi-operand memory operand, like the following example on PowerPC (will be committed as a follow-on patch): def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst), "stwu $rS, $dst", LdStStoreUpd, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff), (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>; Here, the pair of "ptroff" and "ptrreg" operands is matched onto the complex operand "dst" of class "memri" in the "STWU" instruction. Approved by Jakob Stoklund Olesen. llvm-svn: 177428
* TableGen fix for the new machine model.Andrew Trick2013-03-181-4/+6
| | | | | | | | Properly handle cases where a group of instructions have different SchedRW lists with the same itinerary class. This was supposed to work, but I left in an early break. llvm-svn: 177317
* Extract a method.Jakob Stoklund Olesen2013-03-182-41/+42
| | | | | | | This computes the type of an instruction operand or result based on the records in the instruction's ins and outs lists. llvm-svn: 177244
* Use ArrayRef<MVT::SimpleValueType> when possible.Jakob Stoklund Olesen2013-03-176-10/+10
| | | | | | | Not passing vector references around makes it possible to use SmallVector in most places. llvm-svn: 177235
* Machine model. Allow mixed itinerary classes and SchedRW lists.Andrew Trick2013-03-163-205/+174
| | | | | | | | | | | | | We always supported a mixture of the old itinerary model and new per-operand model, but it required a level of indirection to map itinerary classes to SchedRW lists. This was done for ARM A9. Now we want to define x86 SchedRW lists, with the goal of removing its itinerary classes, but still support the itineraries in the mean time. When I original developed the model, Atom did not have itineraries, so there was no reason to expect this requirement. llvm-svn: 177226
* Add SchedRW as an Instruction field.Jakob Stoklund Olesen2013-03-151-6/+6
| | | | | | | | | | | | | Don't require instructions to inherit Sched<...>. Sometimes it is more convenient to say: let SchedRW = ... in { ... } Which is now possible. llvm-svn: 177199
* Fix r177112: Add ProcResGroup.Andrew Trick2013-03-141-1/+3
| | | | | | This is the other half of r177122 that I meant to commit at the same time. llvm-svn: 177123
* MachineModel: Add a ProcResGroup class.Andrew Trick2013-03-142-12/+92
| | | | | | | | | | | | | | | | | This allows abitrary groups of processor resources. Using something in a subset automatically counts againts the superset. Currently, this only works if the superset is also a ProcResGroup as opposed to a SuperUnit. This allows SandyBridge to be expressed naturally, which will be checked in shortly. def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; def SBPort23 : ProcResGroup<[SBPort2, SBPort3]>; def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; llvm-svn: 177112
* Fixes disassembler crashes on 2013 Haswell RTM instructions.Kevin Enderby2013-03-111-0/+11
| | | | | | rdar://13318048 llvm-svn: 176828
* MIsched machine model: tablegen subtarget emitter improvement.Andrew Trick2013-03-011-1/+14
| | | | | | | | Fix the way resources are counted. I'm taking some time to cleanup the way MachineScheduler handles in-order machine resources. Eventually we'll need more PPC/Atom test cases in tree. llvm-svn: 176390
* [TableGen] Fix ICE on MSVC 2012 Release builds.Michael J. Spencer2013-02-261-1/+3
| | | | llvm-svn: 176125
* Fix for bug 15246 -- out-of-bound error in the TableGen backend, ↵Jyotsna Verma2013-02-141-5/+4
| | | | | | CodeGenMapTable.cpp. llvm-svn: 175185
* PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIADavid Peixotto2013-02-131-0/+1
| | | | | | | Fixed bug in tablegen conversion when source pseudo instruction has a different number of arguments than the destination instruction. llvm-svn: 175066
* Added 0x0D to 2-byte opcode extension table for prefetch* variantsKay Tiong Khoo2013-02-121-0/+1
| | | | | | | Fixed decode of existing 3dNow prefetchw instruction Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs llvm-svn: 174920
* Allow targets to add custom asm operand matching logic.Jim Grosbach2013-02-061-0/+9
| | | | | | | | | | For example, ARM has several instructions with a literal '#0' immediate in the syntax that's not represented as an actual operand. The asm matcher is expected a token operand, but the parser will have created an immediate operand. This is currently handled by dedicated per-instruction C++ munging of the ParsedAsmOperand list, but will be better handled by this hook. llvm-svn: 174487
* Fix commentsEli Bendersky2013-02-051-1/+1
| | | | llvm-svn: 174390
* This patch that sets the EmitAlias flag in td files Jack Carter2013-02-051-1/+4
| | | | | | | | | | | | | and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
* MachineModel: Inconsequential TableGen SubtargetEmitter fix.Andrew Trick2013-02-011-1/+15
| | | | | | | | Drive by fix. I noticed some missing logic that might bite future users. This shouldn't affect the final output on currently modeled targets. llvm-svn: 174142
* Clarify intent.Jakob Stoklund Olesen2013-01-311-0/+6
| | | | llvm-svn: 174068
* Add AArch64 as an experimental target.Tim Northover2013-01-311-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. llvm-svn: 174054
* Use the AttributeSet instead of AttributeWithIndex.Bill Wendling2013-01-271-7/+6
| | | | | | | In the future, AttributeWithIndex won't be used anymore. Besides, it exposes the internals of the AttributeSet to outside users, which isn't goodness. llvm-svn: 173606
* [ms-inline asm] Address the FIXME in AsmParser.cpp.Chad Rosier2013-01-151-4/+8
| | | | | | | | | | // FIXME: Constraints are hard coded to 'm', but we need an 'r' // constraint for addressof. This needs to be cleaned up! Test cases are already in place. Specifically, clang/test/CodeGen/ms-inline-asm.c t15(), t16(), and t24(). llvm-svn: 172569
* Support for half intrinsics. Pushes MMX into slower encoding path.Michael Ilseman2013-01-111-18/+20
| | | | llvm-svn: 172159
* TableGen: Keep track of superclass reference ranges.Jordan Rose2013-01-101-2/+4
| | | | | | | | | | def foo : bar; ~~~ This allows us to produce more precise diagnostics about a certain superclass, and even provide fixits. llvm-svn: 172085
* Remove locale-dependence of enum mangling and use existing function.Tim Northover2013-01-101-14/+10
| | | | llvm-svn: 172077
* Make TableGen mangle operand method names before putting in enum.Tim Northover2013-01-101-2/+13
| | | | | | | | | The purpose of this patch is to allow PredicateMethods to be set to something like "isUImm<8>", calling a C++ template method to reduce code duplication. For this to work, the PredicateMethod must be mangled into a valid C++ identifier for insertion into an enum. llvm-svn: 172073
* Check whether MCInst operand isImm before calling getImm.Tim Northover2013-01-091-4/+10
| | | | | | | | | When processing possible aliases, TableGen assumes that if an operand *can* be an immediate, then it always *will* be. This is incorrect for the AArch64 backend. This patch inserts a check in the generated code to make sure isImm is true first. llvm-svn: 171972
* MIsched: add an ILP window property to machine model.Andrew Trick2013-01-091-0/+1
| | | | | | | | | | This was an experimental option, but needs to be defined per-target. e.g. PPC A2 needs to aggressively hide latency. I converted some in-order scheduling tests to A2. Hal is working on more test cases. llvm-svn: 171946
* Sort a few more #include lines in tools/... unittests/... and utils/...Chandler Carruth2013-01-021-3/+2
| | | | llvm-svn: 171363
* TableGen/FixedLenDecoderEmitter.cpp: Fix a potential mask overflow in ↵NAKAMURA Takumi2012-12-261-1/+1
| | | | | | | | fieldFromInstruction(). Reported by Yang Yongyong, thanks! llvm-svn: 171101
* Added 6 more value types: v32i1, v64i1, v32i16, v32i8, v64i8, v8f64Elena Demikhovsky2012-12-241-0/+6
| | | | llvm-svn: 171026
* Change 'AttrVal' to 'AttrKind' to better reflect that it's a kind of ↵Bill Wendling2012-12-221-1/+1
| | | | | | attribute instead of the value of the attribute. llvm-svn: 170972
* Fix an uninitialized member variable, found by -fsanitize=bool.Richard Smith2012-12-201-7/+8
| | | | llvm-svn: 170627
* MC: Add MCInstrDesc::mayAffectControlFlow() method.Jim Grosbach2012-12-191-5/+5
| | | | | | | | | MC disassembler clients (LLDB) are interested in querying if an instruction may affect control flow other than by virtue of being an explicit branch instruction. For example, instructions which write directly to the PC on some architectures. llvm-svn: 170610
* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-194-1020/+0
| | | | llvm-svn: 170578
* Rename the 'Attributes' class to 'Attribute'. It's going to represent a ↵Bill Wendling2012-12-191-6/+6
| | | | | | single attribute in the future. llvm-svn: 170502
* Fix PR14568: Avoid the DFA packetizer from making an invalid readAnshuman Dasgupta2012-12-101-1/+10
| | | | | | | | | | beyond array bounds. No test case since I cannot reproduce an ICE with this bug. According to Carlos -- the bug reporter -- a segfault occurs only when LLVM is compiled with a specific version of GCC. llvm-svn: 169783
* s/AttrListPtr/AttributeSet/g to better label what this class is going to be ↵Bill Wendling2012-12-071-5/+5
| | | | | | in the near future. llvm-svn: 169651
* RegisterPresssureTracker: Track live physical register by unit.Andrew Trick2012-12-051-2/+6
| | | | | | | | This is much simpler to reason about, more efficient, and fixes some corner cases involving implicit super-register defs. Fixed rdar://12797931. llvm-svn: 169425
* RegisterPressure API. Add support for physical register units.Andrew Trick2012-12-053-11/+115
| | | | | | | | | | | | | At build-time register pressure was always computed in terms of register units. But the compile-time API was expressed in terms of register classes because it was intended for virtual registers (and physical register units weren't yet used anywhere in codegen). Now that the codegen uses physreg units consistently, prepare for tracking register pressure also in terms of live units, not live registers. llvm-svn: 169360
* Copy clang/Driver/<Option parsing stuff> to llvm.Michael J. Spencer2012-12-054-1/+276
| | | | llvm-svn: 169344
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