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* [CodeGen] Add OPC_MoveChild0-OPC_MoveChild7 opcodes to isel matching tables ↵Craig Topper2016-05-021-3/+10
| | | | | | to optimize table size. Shaves about 12K off the X86 matcher table. llvm-svn: 268209
* TableGen: Produce CoveredBySubRegs summary for register classesMatthias Braun2016-04-283-3/+9
| | | | | | This will be used in the upcoming "DetectDeadLanes" pass. llvm-svn: 267850
* TargetRegisterInfo: Introduce reverseComposeSubRegIndexLaneMask()Matthias Braun2016-04-281-12/+29
| | | | | | | | | This function performs the reverse computation of composeSubRegIndexLaneMask(). It will be used in the upcoming "DetectDeadLanes" pass. llvm-svn: 267849
* TableGen: Support lanemasks for classes without subregistersMatthias Braun2016-04-281-38/+50
| | | | | | | | | | | | | Previously using lanemasks on registers without any subregisters was not well defined. This commit extends TargetRegisterInfo/tablegen to: - Report a lanemask of 1 for regclasses without subregisters - Do the right thing when mapping a 0/1 lanemask from a class without subregisters into a class with subregisters in TargetRegisterInfo::composeSubRegIndexLaneMasks(). This will be used in the upcoming "DetectDeadLanes" patch. llvm-svn: 267848
* Split IntrReadArgMem into IntrReadMem and IntrArgMemOnlyNicolai Haehnle2016-04-212-9/+5
| | | | | | | | | | | | | | | | | | Summary: IntrReadWriteArgMem simply becomes IntrArgMemOnly. So there are fewer intrinsic properties that express their orthogonality better, and correspond more closely to the corresponding IR attributes. Suggested by: Philip Reames Reviewers: joker.eph, reames, tstellarAMD Subscribers: jholewinski, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19291 llvm-svn: 267021
* Add LLVMGetAttrKindID in the C API in order to facilitate migration away ↵Amaury Sechet2016-04-201-0/+23
| | | | | | | | | | | | | | | | | from LLVMAttribute Summary: LLVMAttribute has outlived its utility and is becoming a problem for C API users that what to use all the LLVM attributes. In order to help moving away from LLVMAttribute in a smooth manner, this diff introduce LLVMGetAttrKindIDInContext, which can be used instead of the enum values. See D18749 for reference. Reviewers: Wallbraker, whitequark, joker.eph, echristo, rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19081 llvm-svn: 266842
* Add IntrWrite[Arg]Mem intrinsic propertyNicolai Haehnle2016-04-194-9/+40
| | | | | | | | | | | | | | | | | | | | | | Summary: This property is used to mark an intrinsic that only writes to memory, but neither reads from memory nor has other side effects. An example where this is useful is the llvm.amdgcn.buffer.store.format.* intrinsic, which corresponds to a store instruction that goes through a special buffer descriptor rather than through a plain pointer. With this property, the intrinsic should still be handled as having side effects at the LLVM IR level, but machine scheduling can make smarter decisions. Reviewers: tstellarAMD, arsenm, joker.eph, reames Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18291 llvm-svn: 266826
* [TableGen] Make an error message slightly more informativeNicolai Haehnle2016-04-191-2/+9
| | | | | | | | | | Reviewers: ab, spop, stoklund Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19192 llvm-svn: 266823
* [NFC] Header cleanupMehdi Amini2016-04-1810-14/+4
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* Declare MVT::SimpleValueType as an int8_t sized enum. This removes 400 bytes ↵Craig Topper2016-04-171-3/+5
| | | | | | | | | | from TargetLoweringBase and probably other places. This required changing several places to print VT enums as strings instead of raw ints since the proper method to use to print became ambiguous. This is probably an improvement anyway. This also appears to save ~8K from an x86 self host build of llc. llvm-svn: 266562
* Update and fix LLVM_ENABLE_MODULES:Richard Smith2016-04-161-4/+0
| | | | | | | | | | | | | | | | 1) We need to add this flag prior to adding any other, in case the user has specified a -fmodule-cache-path= flag in their custom CXXFLAGS. Such a flag causes -Werror builds to fail, and thus all config checks fail, until we add the corresponding -fmodules flag. The modules selfhost bot does this, for instance. 2) Delete module maps that were putting .cpp files into modules. 3) Enable -fmodules-local-submodule-visibility, to get proper module visibility rules applied across submodules of the same module. Disable -fmodules for C builds, since that flag is not available there. llvm-svn: 266502
* Revert "Add LLVMGetAttrKindIDInContext in the C API in order to facilitate ↵Amaury Sechet2016-04-131-23/+0
| | | | | | | | migration away from LLVMAttribute" This reverts commit 0bcfd95c268bcb180a525e1837e84475df8acdc7. llvm-svn: 266259
* Add LLVMGetAttrKindIDInContext in the C API in order to facilitate migration ↵Amaury Sechet2016-04-131-0/+23
| | | | | | | | | | | | | | away from LLVMAttribute Summary: LLVMAttribute has outlived its utility and is becoming a problem for C API users that what to use all the LLVM attributes. In order to help moving away from LLVMAttribute in a smooth manner, this diff introduce LLVMGetAttrKindIDInContext, which can be used instead of the enum values. Reviewers: Wallbraker, whitequark, joker.eph, echristo Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18749 llvm-svn: 266257
* Minor code cleanup. NFC.Junmo Park2016-04-121-2/+2
| | | | llvm-svn: 266045
* [TableGen] AsmMatcherEmitter.cpp: replace a sequence of "if" to "switch" in ↵Valery Pykhtin2016-04-051-2/+6
| | | | | | | | emitValidateOperandClass. Differential Revision: http://reviews.llvm.org/D18394 llvm-svn: 265412
* [TableGen] more helpful error message in MapTableEmitterNicolai Haehnle2016-03-101-2/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D17275 llvm-svn: 263148
* [CodeGen] Add space-optimized EmitMergeInputChains1_2 to the DAG isel ↵Craig Topper2016-03-071-2/+2
| | | | | | matching tables. Shaves about 5100 bytes from the X86 matcher table. NFC llvm-svn: 262815
* TableGen: Accept itinerary data when checking for schedmodel completenessMatthias Braun2016-03-031-4/+4
| | | | llvm-svn: 262548
* TableGen: Display helpfull message for incomplete models.Matthias Braun2016-03-011-1/+7
| | | | llvm-svn: 262399
* TableGen: Check scheduling models for completenessMatthias Braun2016-03-012-0/+47
| | | | | | | | | | | | | | | | | | | | | | TableGen checks at compiletime that for scheduling models with "CompleteModel = 1" one of the following holds: - Is marked with the hasNoSchedulingInfo flag - The instruction is a subclass of Sched - There are InstRW definitions in the scheduling model Typical steps necessary to complete a model: - Ensure all pseudo instructions that are expanded before machine scheduling (usually everything handled with EmitYYY() functions in XXXTargetLowering). - If a CPU does not support some instructions mark the corresponding resource unsupported: "WriteRes<WriteXXX, []> { let Unsupported = 1; }". - Add missing scheduling information. Differential Revision: http://reviews.llvm.org/D17747 llvm-svn: 262384
* TableGen: Add hasNoSchedulingInfo to instructionsMatthias Braun2016-03-013-1/+4
| | | | | | | | | | | | | This introduces a new flag that indicates that a specific instruction will never be present when the MachineScheduler runs and therefore needs no scheduling information. This is in preparation for an upcoming commit which checks completeness of a scheduling model when tablegen runs. Differential Revision: http://reviews.llvm.org/D17728 llvm-svn: 262383
* [TableGen] AsmMatcher: Skip optional operands in the midle of instruction if ↵Nikolay Haustov2016-03-011-14/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | it is not present Previosy, if actual instruction have one of optional operands then other optional operands listed before this also should be presented. For example instruction v_fract_f32 v0, v1, mul:2 have one optional operand - OMod and do not have optional operand clamp. Previously this was not allowed because clamp is listed before omod in AsmString: string AsmString = "v_fract_f32$vdst, $src0_modifiers$clamp$omod"; Making this work required some hacks (both OMod and Clamp match classes have same PredicateMethod). Now, if MatchInstructionImpl meets formal optional operand that is not presented in actual instruction it skips this formal operand and tries to match current actual operand with next formal. Patch by: Sam Kolton Review: http://reviews.llvm.org/D17568 [AMDGPU] Assembler: Check immediate types for several optional operands in predicate methods With this change you should place optional operands in order specified by asm string: clamp -> omod offset -> glc -> slc -> tfe Fixes for several tests. Depends on D17568 Patch by: Sam Kolton Review: http://reviews.llvm.org/D17644 llvm-svn: 262314
* AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . ↵Igor Breger2016-02-251-16/+20
| | | | | | | | Change memory operand parser handling. Differential Revision: http://reviews.llvm.org/D17564 llvm-svn: 261862
* Fix commentXinliang David Li2016-02-231-1/+1
| | | | llvm-svn: 261672
* [X86] Remove some unused encoding checks from the disassembler table building.Craig Topper2016-02-201-4/+0
| | | | llvm-svn: 261418
* [TableGen,X86] Add NDEBUG check to a variable initialization that's only ↵Craig Topper2016-02-181-0/+2
| | | | | | used by asserts. NFC llvm-svn: 261188
* [TableGen,X86] Remove extra optional operand from RawFrm. RawFrm with 2 ↵Craig Topper2016-02-181-3/+1
| | | | | | immediates is handled by RawFrmImm8/RawFrmImm16. llvm-svn: 261187
* [TableGen] Fix inconsistent spacing. NFCCraig Topper2016-02-161-2/+2
| | | | llvm-svn: 260935
* [TableGen] Stop passing by reference an integer that doesn't get modified. NFCCraig Topper2016-02-162-2/+2
| | | | llvm-svn: 260934
* [TableGen] Remove unused member variable. NFCCraig Topper2016-02-162-3/+0
| | | | llvm-svn: 260933
* [TableGen] Use range-based for loop. NFCCraig Topper2016-02-161-2/+2
| | | | llvm-svn: 260928
* [TableGen] Remove constant string argument from a method that's only called ↵Craig Topper2016-02-141-5/+5
| | | | | | once. We can just hardcode the string inside. There already other things that make the method not reusable. NFC llvm-svn: 260840
* [TableGen] Fix comment about 64-bit type I missed when I removed the ↵Craig Topper2016-02-131-1/+1
| | | | | | underlying type in r260808. llvm-svn: 260830
* [TableGen] Use range-based for loops. NFCCraig Topper2016-02-132-131/+106
| | | | llvm-svn: 260809
* No need to make the subtarget feature bit enum a uint64_t. This was a ↵Craig Topper2016-02-131-1/+1
| | | | | | leftover from when the feature bit enum contained masks instead of bit indices. llvm-svn: 260808
* [TableGen] Use range-based for loops. NFCCraig Topper2016-02-111-10/+7
| | | | llvm-svn: 260502
* [TableGen] Don't call emitSourceFileHeader a second time in the middle of ↵Craig Topper2016-02-111-3/+1
| | | | | | the output file. llvm-svn: 260501
* [TableGen] Whitespace cleanup in output file. NFCCraig Topper2016-02-111-14/+14
| | | | llvm-svn: 260500
* [TableGen] Simplify code slightly. NFCCraig Topper2016-02-111-6/+3
| | | | llvm-svn: 260499
* SelectionDAG: Make Properties a field of SDPatternOperatorMatt Arsenault2016-02-101-1/+1
| | | | | | | | | Currently you can't specify node properties like commutativity on a PatFrag. If you want to create a PatFrag on a commutative node with a hasOneUse predicate, this enables you to specify that the PatFrag is also commutable. llvm-svn: 260404
* TableGen: Add IsOptional field to AsmOperandClassTom Stellard2016-02-051-1/+15
| | | | | | | | | | | | | | | Summary: This makes it possible to specify some operands as optional to the AsmMatcher. Setting this field to true will prevent the AsmMatcher from emitting 'too few operands' errors when there are missing optional operands. Reviewers: olista01, ab Subscribers: nhaustov, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15755 llvm-svn: 259913
* Unify the target opcode enum in TargetOpcodes.h and the FixedInstrs array inDavid L Kreitzer2016-02-031-12/+2
| | | | | | | | CodeGenTarget.cpp to avoid the ordering dependence. NFCI. Differential Revision: http://reviews.llvm.org/D16826 llvm-svn: 259726
* Minor performance tweaks to llvm-tblgen (and a few that might be a good idea)Reid Kleckner2016-02-032-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds a reserve call to an expensive function (`llvm::LoadIntrinsics`), and may fix a few other low hanging performance fruit (I've put them in comments for now, so we can discuss). **Motivation:** As I'm sure other developers do, when I build LLVM, I build the entire project with the same config (`Debug`, `MinSizeRel`, `Release`, or `RelWithDebInfo`). However, the `Debug` config also builds llvm-tblgen in `Debug` mode. Later build steps that run llvm-tblgen then can actually be the slowest steps in the entire build. Nobody likes slow builds. Reviewers: rnk, dblaikie Differential Revision: http://reviews.llvm.org/D16832 Patch by Alexander G. Riccio llvm-svn: 259683
* [TableGen] Add 'register alternative name matching' supportDylan McKay2016-02-031-0/+34
| | | | | | | | | | | | | | | | | Summary: This adds a new attribute which targets can set in TableGen which causes a function to be generated which matches register alternative names. This is very similar to `ShouldEmitMatchRegisterName`, except it works on alt names. This patch is currently used by the out of tree part of the AVR backend. It reduces code duplication greatly, and has the effect that you do not need to hardcode altname to register mappings in C++. It will not work on targets which have registers which share the same aliases. Reviewers: stoklund, arsenm, dsanders, hfinkel, vkalintiris Subscribers: hfinkel, dylanmckay, llvm-commits Differential Revision: http://reviews.llvm.org/D16312 llvm-svn: 259636
* Fix Clang-tidy readability-redundant-control-flow warnings; other minor fixes.Eugene Zelenko2016-02-021-11/+5
| | | | | | Differential revision: http://reviews.llvm.org/D16793 llvm-svn: 259539
* [TableGen] Store result of getInstructionsByEnumValue in an ArrayRef instead ↵Craig Topper2016-02-015-15/+11
| | | | | | of accidentally copying to a vector. llvm-svn: 259336
* No need to use utostr/utohexstr when writing into a raw_ostream. NFCCraig Topper2016-01-311-24/+30
| | | | llvm-svn: 259314
* [llvm-tblgen] Avoid StringMatcher for GCC and MS builtin namesReid Kleckner2016-01-271-91/+56
| | | | | | | | | | | | | | | This brings the compile time of Function.cpp from ~40s down to ~4s for me locally. It also shaves off about 400KB of object file size in a release+asserts build. I also realized that the AMDGPU backend does not have any GCC builtin names to match, so the extra lookup was a no-op. I removed it to silence a zero-length string table array warning. There should be no functional change here. This change really ends the story of PR11951. llvm-svn: 258897
* [llvm-tblgen] Stop emitting the intrinsic name matching codeReid Kleckner2016-01-261-60/+0
| | | | | | | | | The AMDGPU backend was the last user of the old StringMatcher recognition code. Move it over to the new lookupLLVMIntrinsicName funciton, which is now improved to handle all of the interesting edge cases exposed by AMDGPU intrinsic names. llvm-svn: 258875
* Remove autoconf supportChris Bieneman2016-01-261-18/+0
| | | | | | | | | | | | | | | | Summary: This patch is provided in preparation for removing autoconf on 1/26. The proposal to remove autoconf on 1/26 was discussed on the llvm-dev thread here: http://lists.llvm.org/pipermail/llvm-dev/2016-January/093875.html "I felt a great disturbance in the [build system], as if millions of [makefiles] suddenly cried out in terror and were suddenly silenced. I fear something [amazing] has happened." - Obi Wan Kenobi Reviewers: chandlerc, grosbach, bob.wilson, tstellarAMD, echristo, whitequark Subscribers: chfast, simoncook, emaste, jholewinski, tberghammer, jfb, danalbert, srhines, arsenm, dschuff, jyknight, dsanders, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D16471 llvm-svn: 258861
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