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* Move most user of TargetMachine::getDataLayout to the Module oneMehdi Amini2015-07-161-4/+4
| | | | | | | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. This patch is quite boring overall, except for some uglyness in ASMPrinter which has a getDataLayout function but has some clients that use it without a Module (llmv-dsymutil, llvm-dwarfdump), so some methods are taking a DataLayout as parameter. Reviewers: echristo Subscribers: yaron.keren, rafael, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11090 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 242386
* [TableGen] Improve decoding options for non-orthogonal instructionsPetr Pavlu2015-07-152-34/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When FixedLenDecoder matches an input bitpattern of form [01]+ with an instruction bitpattern of form [01?]+ (where 0/1 are static bits and ? are mixed/variable bits) it passes the input bitpattern to a specific instruction decoder method which then makes a final decision whether the bitpattern is a valid instruction or not. This means the decoder must handle all possible values of the variable bits which sometimes leads to opcode rewrites in the decoder method when the instructions are not fully orthogonal. The patch provides a way for the decoder method to say that when it returns Fail it does not necessarily mean the bitpattern is invalid, but rather that the bitpattern is definitely not an instruction that is recognized by the decoder method. The decoder can then try to match the input bitpattern with other possible instruction bitpatterns. For example, this allows to solve a situation on AArch64 where the `MSR (immediate)` instruction has form: 1101 0101 0000 0??? 0100 ???? ???1 1111 but not all values of the ? bits are allowed. The rejected values should be handled by the `extended MSR (register)` instruction: 1101 0101 000? ???? ???? ???? ???? ???? The decoder will first try to decode an input bitpattern that matches both bitpatterns as `MSR (immediate)` but currently this puts the decoder method of `MSR (immediate)` into a situation when it must be able to decode all possible values of the ? bits, i.e. it would need to rewrite the instruction to `MSR (register)` when it is not `MSR (immediate)`. The patch allows to specify that the decoder method cannot determine if the instruction is valid for all variable values. The decoder method can simply return Fail when it knows it is definitely not `MSR (immediate)`. The decoder will then backtrack the decoding and find that it can match the input bitpattern with the more generic `MSR (register)` bitpattern too. Differential Revision: http://reviews.llvm.org/D7174 llvm-svn: 242274
* Fix comment typoPetr Pavlu2015-07-141-1/+1
| | | | | | Test commit access. llvm-svn: 242128
* AVX-512: Added all AVX-512 forms of Vector Convert for Float/Double/Int/Long ↵Elena Demikhovsky2015-07-131-2/+24
| | | | | | | | | | | | types. In this patch I have only encoding. Intrinsics and DAG lowering will be in the next patch. I temporary removed the old intrinsics test (just to split this patch). Half types are not covered here. Differential Revision: http://reviews.llvm.org/D11134 llvm-svn: 242023
* MC: Remove MCSubtargetInfo() default constructorDuncan P. N. Exon Smith2015-07-101-8/+7
| | | | | | | | | | | | | | | | | | | | | Force all creators of `MCSubtargetInfo` to immediately initialize it, merging the default constructor and the initializer into an initializing constructor. Besides cleaning up the code a little, this makes it clear that the initializer is never called again later. Out-of-tree backends need a trivial change: instead of calling: auto *X = new MCSubtargetInfo(); InitXYZMCSubtargetInfo(X, ...); return X; they should call: return createXYZMCSubtargetInfoImpl(...); There's no real functionality change here. llvm-svn: 241957
* Target RegisterInfo: devirtualize TargetFrameLoweringJF Bastien2015-07-101-0/+12
| | | | | | | | | | | | | Summary: The target frame lowering's concrete type is always known in RegisterInfo, yet it's only sometimes devirtualized through a static_cast. This change adds an auto-generated static function <Target>GenRegisterInfo::getFrameLowering(const MachineFunction &MF) which does this devirtualization, and uses this function in all targets which can. This change was suggested by sunfish in D11070 for WebAssembly, I figure that I may as well improve the other targets while I'm here. Subscribers: sunfish, ted, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11093 llvm-svn: 241921
* Rename llvm.frameescape and llvm.framerecover to localescape and localrecoverReid Kleckner2015-07-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Initially, these intrinsics seemed like part of a family of "frame" related intrinsics, but now I think that's more confusing than helpful. Initially, the LangRef specified that this would create a new kind of allocation that would be allocated at a fixed offset from the frame pointer (EBP/RBP). We ended up dropping that design, and leaving the stack frame layout alone. These intrinsics are really about sharing local stack allocations, not frame pointers. I intend to go further and add an `llvm.localaddress()` intrinsic that returns whatever register (EBP, ESI, ESP, RBX) is being used to address locals, which should not be confused with the frame pointer. Naming suggestions at this point are welcome, I'm happy to re-run sed. Reviewers: majnemer, nicholas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11011 llvm-svn: 241633
* Reverting r241058 because it's causing buildbot failures.Ranjeet Singh2015-06-301-30/+26
| | | | llvm-svn: 241061
* There are a few places where subtarget features are stillRanjeet Singh2015-06-301-26/+30
| | | | | | | | | represented by uint64_t, this patch replaces these usages with the FeatureBitset (std::bitset) type. Differential Revision: http://reviews.llvm.org/D10542 llvm-svn: 241058
* MIR Serialization: Serialize the register mask machine operands.Alex Lorenz2015-06-291-0/+22
| | | | | | | | | | | | | | | | | This commit implements serialization of the register mask machine operands. This commit serializes only the call preserved register masks that are defined by a target, it doesn't serialize arbitrary register masks. This commit also extends the TargetRegisterInfo class and TableGen so that the users of TRI can get the list of all the call preserved register masks and their names. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10673 llvm-svn: 240966
* AVX-512: Added all SKX forms of GATHER instructions.Elena Demikhovsky2015-06-281-0/+6
| | | | | | | Added intrinsics. Added encoding and tests. llvm-svn: 240905
* Avoid a Symbol -> Name -> Symbol conversion.Rafael Espindola2015-06-221-1/+2
| | | | | | | | | | | | | | Before this we were producing a TargetExternalSymbol from a MCSymbol. That meant extracting the symbol name and fetching the symbol again down the pipeline. This patch adds a DAG.getMCSymbol that lets the MCSymbol pass unchanged on the DAG. Doing so removes the need for MO_NOPREFIX and fixes the root cause of pr23900, allowing r240130 to be committed again. llvm-svn: 240300
* [CodeGen] Introduce a FAULTING_LOAD_OP pseudo-op.Sanjoy Das2015-06-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This instruction encodes a loading operation that may fault, and a label to branch to if the load page-faults. The locations of potentially faulting loads and their "handler" destinations are recorded in a FaultMap section, meant to be consumed by LLVM's clients. Nothing generates FAULTING_LOAD_OP instructions yet, but they will be used in a future change. The documentation (FaultMaps.rst) needs improvement and I will update this diff with a more expanded version shortly. Depends on D10196 Reviewers: rnk, reames, AndyAyers, ab, atrick, pgavlin Reviewed By: atrick, pgavlin Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10197 llvm-svn: 239740
* Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and ↵Daniel Sanders2015-06-101-4/+5
| | | | | | | | | | | | | | | | | | create*MCSubtargetInfo(). NFC. Summary: This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: rafael Reviewed By: rafael Subscribers: rafael, ted, jfb, llvm-commits, rengolin, jholewinski Differential Revision: http://reviews.llvm.org/D10311 llvm-svn: 239467
* X86-MPX: Implemented encoding for MPX instructions.Elena Demikhovsky2015-06-091-0/+3
| | | | | | Added encoding tests. llvm-svn: 239403
* [TableGen] Remove unnecessary default constructed SMLoc that just existed to ↵Craig Topper2015-06-081-5/+1
| | | | | | return. Instead just call the default constructor in the return. llvm-svn: 239277
* [TableGen] Use range-based for loop. NFCCraig Topper2015-06-081-3/+2
| | | | llvm-svn: 239276
* [TableGen] Remove unnecessary extern declaration that's already in an ↵Craig Topper2015-06-081-2/+0
| | | | | | included header file. llvm-svn: 239275
* [TableGen] Use the SMLoc header file instead of SourceMgr header file in a ↵Craig Topper2015-06-081-1/+2
| | | | | | couple places. NFC llvm-svn: 239274
* [TableGen] Rename ListInit::getSize to just 'size' to be more consistent.Craig Topper2015-06-025-27/+26
| | | | llvm-svn: 238806
* [TableGen] Use range-based for loops. NFC.Craig Topper2015-06-023-22/+18
| | | | llvm-svn: 238805
* Replace push_back(Constructor(foo)) with emplace_back(foo) for non-trivial typesBenjamin Kramer2015-05-299-50/+37
| | | | | | | | | | | | | | | | | | | | If the type isn't trivially moveable emplace can skip a potentially expensive move. It also saves a couple of characters. Call sites were found with the ASTMatcher + some semi-automated cleanup. memberCallExpr( argumentCountIs(1), callee(methodDecl(hasName("push_back"))), on(hasType(recordDecl(has(namedDecl(hasName("emplace_back")))))), hasArgument(0, bindTemporaryExpr( hasType(recordDecl(hasNonTrivialDestructor())), has(constructExpr()))), unless(isInTemplateInstantiation())) No functional change intended. llvm-svn: 238602
* [TableGen][AsmMatcherEmitter] Only parse isolated tokens as registers.Ahmed Bougacha2015-05-291-4/+22
| | | | | | | | | | | | | | Fixes PR23455, where, when TableGen generates the matcher from the AsmString, it splits "cmp${cc}ss" into tokens, and the "ss" suffix is recognized as the SS register. I can't think of a situation where that's a feature, not a bug, hence: when a token is "isolated", i.e., it is followed and preceded by separators, it shouldn't be parsed as a register. Differential Revision: http://reviews.llvm.org/D9844 llvm-svn: 238536
* [TableGen][AsmMatcherEmitter] Factor out AsmOperand creation. NFC.Ahmed Bougacha2015-05-291-8/+15
| | | | llvm-svn: 238534
* Add support for the convergent flag at the MC and MachineInstr levels.Owen Anderson2015-05-283-31/+34
| | | | llvm-svn: 238450
* Expand the Flags field of MCInstrDesc to 64 bits, while simultaneouslyOwen Anderson2015-05-281-2/+2
| | | | | | | | | | | shrinking the Size and NumDefs fields to offset the size growth, and reordering the fields to preserve a good packing. This is necessary in the short term for adding a convergent flag, and simultaneously future-proofs us against more flags being added in the future. llvm-svn: 238445
* Add initial support for the convergent attribute.Owen Anderson2015-05-263-1/+16
| | | | llvm-svn: 238264
* AsmMatcherEmitter: Add an option to override custom converters for InstAliasTom Stellard2015-05-261-3/+12
| | | | | | | | | | | | | | | | | If there is an InstAlias defined for an instruction that had a custom converter (AsmMatchConverter), then when the alias is matched, the custom converter will be used rather than the converter generated by the InstAlias. This patch adds the UseInstAsmMatchConverter field to the InstAlias class, which allows you to override this behavior and force the converter generated by the InstAlias to be used. This is required for some future improvemnts to the R600 assembler. Differential Revision: http://reviews.llvm.org/D9083 llvm-svn: 238210
* Use std::bitset for SubtargetFeatures.Michael Kuperstein2015-05-264-46/+41
| | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
* This patch adds support for the vector quadword add/sub instructions introducedKit Barton2015-05-251-1/+3
| | | | | | | | | | | | | | | | | | | | in POWER8: vadduqm vaddeuqm vaddcuq vaddecuq vsubuqm vsubeuqm vsubcuq vsubecuq In addition to adding the instructions themselves, it also adds support for the v1i128 type for intrinsics (Intrinsics.td, Function.cpp, and IntrinsicEmitter.cpp). http://reviews.llvm.org/D9081 llvm-svn: 238144
* [TableGen] Remove ListInit::size() in favor of getSize() which does the same ↵Craig Topper2015-05-141-2/+2
| | | | | | thing and is already used in most places. NFC. llvm-svn: 237341
* [TableGen] Replace some calls to ListInit::getSize() with ListInit::empty() ↵Craig Topper2015-05-142-3/+3
| | | | | | if it was just comparing to 0. NFC. llvm-svn: 237340
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-133-5/+5
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-134-41/+46
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-134-46/+41
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* Fix tablegen's PrintFatalError function to run registered fileJames Y Knight2015-05-115-28/+24
| | | | | | | | | | | | | | | cleanups. Also, change code in tablegen which printed a message and then called "exit(1)" to use PrintFatalError, instead. This fixes instances where an empty output file was left behind after a failed tablegen invocation, which would confuse subsequent ninja runs into not attempting to rebuild. Differential Revision: http://reviews.llvm.org/D9608 llvm-svn: 237058
* [TableGen] Don't leak Expanders and Operators in SetTheory.Craig Topper2015-04-242-3/+3
| | | | llvm-svn: 235697
* [TableGen] Use 'isa' to identify UnsetInits rather than comparing with the ↵Craig Topper2015-04-222-2/+2
| | | | | | singleton object created by UnsetInit::get(). Makes it more consistent with the other types. llvm-svn: 235465
* AVX-512: Added VPMOVx2M instructions for SKX,Elena Demikhovsky2015-04-211-0/+6
| | | | | | fixed encoding of VPMOVM2x. llvm-svn: 235385
* AVX-512: Added VPTESTM and VPTESTNM instructions for SKXElena Demikhovsky2015-04-211-0/+7
| | | | llvm-svn: 235383
* Add support for v1i128 type.Kit Barton2015-04-171-0/+1
| | | | | | | | | | | | The v1i128 type is needed for the quadword add/substract instructions introduced in POWER8. Futhermore, the PowerPC ABI specifies that parameters of type v1i128 are to be passed in a single vector register, while parameters of type i128 are passed in pairs of GPRs. Thus, it is necessary to be able to differentiate between v1i128 and i128 in LLVM. http://reviews.llvm.org/D8564 llvm-svn: 235198
* Change range-based for-loops to be -Wrange-loop-analysis clean.Richard Trieu2015-04-151-1/+1
| | | | | | No functionality change. llvm-svn: 234963
* Use 'override/final' instead of 'virtual' for overridden methodsAlexander Kornienko2015-04-111-3/+3
| | | | | | | | | | | | | | The patch is generated using clang-tidy misc-use-override check. This command was used: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py \ -checks='-*,misc-use-override' -header-filter='llvm|clang' \ -j=32 -fix -format http://reviews.llvm.org/D8925 llvm-svn: 234679
* Use SmallVector instead of std::vector for uniquing X86 disassembler operand ↵Craig Topper2015-04-091-1/+2
| | | | | | sets. The number of operands is a small fixed size. llvm-svn: 234465
* Simplify some printing code by combining new lines onto previous strings. ↵Craig Topper2015-04-091-9/+3
| | | | | | Don't work so hard not to print a comma on the last entry of an array. llvm-svn: 234464
* Don't convert enum to strings just to put them in the uniquing map. Use the ↵Craig Topper2015-04-091-15/+12
| | | | | | enum directly. Only convert to a string for printing. llvm-svn: 234463
* Revert r234389. It really was needed but really should have been cstring ↵Craig Topper2015-04-081-0/+1
| | | | | | instead of string.h llvm-svn: 234390
* Remove unnecessary include. NFCCraig Topper2015-04-081-1/+0
| | | | llvm-svn: 234389
* [TableGen] Prevent invalid code generation when emitting AssemblerPredicate ↵Toma Tabacu2015-04-071-1/+3
| | | | | | | | | | | | | | | | | | | conditions. Summary: The loop which emits AssemblerPredicate conditions also links them together by emitting a '&&'. If the 1st predicate is not an AssemblerPredicate, while the 2nd one is, nothing gets emitted for the 1st one, but we still emit the '&&' because of the 2nd predicate. This generated code looks like "( && Cond2)" and is invalid. Reviewers: dsanders Reviewed By: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D8294 llvm-svn: 234312
* TableGen: Generate more const goodnessMatthias Braun2015-04-011-2/+2
| | | | llvm-svn: 233857
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