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* Fix AllocationPriority not getting set for derived register classes.Matthias Braun2015-03-311-1/+3
| | | | llvm-svn: 233752
* RegAllocGreedy: Allow target to specify register class ordering.Matthias Braun2015-03-313-0/+6
| | | | | | | | | | Specify an allocation order with a register class. This is used by register allocators with a greedy heuristic. This is usefull as it is sometimes beneficial to color more constrained classes first. Differential Revision: http://reviews.llvm.org/D8626 llvm-svn: 233743
* [MCInstPrinter] Enable MCInstPrinter to change its behavior based on theAkira Hatanaka2015-03-273-12/+36
| | | | | | | | | | | | | | | | | | | | per-function subtarget. Currently, code-gen passes the default or generic subtarget to the constructors of MCInstPrinter subclasses (see LLVMTargetMachine::addPassesToEmitFile), which enables some targets (AArch64, ARM, and X86) to change their instprinter's behavior based on the subtarget feature bits. Since the backend can now use different subtargets for each function, instprinter has to be changed to use the per-function subtarget rather than the default subtarget. This patch takes the first step towards enabling instprinter to change its behavior based on the per-function subtarget. It adds a bit "PassSubtarget" to AsmWriter which tells table-gen to pass a reference to MCSubtargetInfo to the various print methods table-gen auto-generates. I will follow up with changes to instprinters of AArch64, ARM, and X86. llvm-svn: 233411
* Revert "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-03-244-41/+46
| | | | | | | | This reverts commit r233055. It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time. llvm-svn: 233068
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-03-244-46/+41
| | | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055
* Another set of missing raw_ostream.h. Still no functional change.Benjamin Kramer2015-03-231-0/+1
| | | | llvm-svn: 232993
* [Tablegen] Attempt to add support for patterns containing nodes with ↵Craig Topper2015-03-201-22/+27
| | | | | | | | | | multiple results. This is needed for AVX512 masked scatter/gather support. The R600 change is necessary to remove a hack that was working around the lack of multiple results. llvm-svn: 232798
* Do not track subregister liveness when it brings no benefitsMatthias Braun2015-03-193-1/+17
| | | | | | | | | | | Some subregisters are only to indicate different access sizes, while not providing any way to actually divide the register up into multiple disjunct parts. Avoid tracking subregister liveness in these cases as it is not beneficial. Differential Revision: http://reviews.llvm.org/D8429 llvm-svn: 232695
* TableGen: Fix register class lane masks being too conservative.Matthias Braun2015-03-181-1/+1
| | | | | | | | | | | | | | When calculating the lanemask of a register class we have to include the masks of subregisters supported by any of the class members, not just the ones supported by all class members. This fixes problems when coalescing towards a subclass with additional subregisters available. The attached testcase works fine as is, but does crash if you enable subregister liveness on x86 without this change applied. llvm-svn: 232652
* Remove many superfluous SmallString::str() calls.Yaron Keren2015-03-181-1/+1
| | | | | | | | | | | | | | | Now that SmallString is a first-class citizen, most SmallString::str() calls are not required. This patch removes a whole bunch of them, yet there are lots more. There are two use cases where str() is really needed: 1) To use one of StringRef member functions which is not available in SmallString. 2) To convert to std::string, as StringRef implicitly converts while SmallString do not. We may wish to change this, but it may introduce ambiguity. llvm-svn: 232622
* Use the variable names from the TargetInstrInfo source when weEric Christopher2015-03-131-5/+7
| | | | | | | reference them in the generated files. A few characters aren't huge here and CFSetupOpcode is much more readable than S0. llvm-svn: 232132
* Add a return after the llvm namespace code for a little extraEric Christopher2015-03-131-3/+3
| | | | | | readability in generated files. llvm-svn: 232131
* Have getRegPressureSetLimit take a MachineFunction so that aEric Christopher2015-03-111-2/+3
| | | | | | we can inspect the subtarget and function when computing values. llvm-svn: 231951
* Teach raw_ostream to accept SmallString.Yaron Keren2015-03-102-3/+3
| | | | | | | | | | | | | | Saves adding .str() call to any raw_ostream << SmallString usage and a small step towards making .str() consistent in the ADTs by removing one of the SmallString::str() use cases, discussion at http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20141013/240026.html I'll update the Phabricator patch http://reviews.llvm.org/D6372 for review of the Twine SmallString support, it's more complex than this one. llvm-svn: 231763
* Improve and simplify EnforceSmallerThan for vector types.Craig Topper2015-03-101-54/+28
| | | | | | Explicitly compare the size of the scalar types and the whole vector size rather than just comparing enum encodings. llvm-svn: 231746
* Remove extra indentation of entire function body. NFC.Craig Topper2015-03-101-140/+140
| | | | llvm-svn: 231745
* TableGen: Use 'enum : uint64_t' for feature flags to fix -WmicrosoftReid Kleckner2015-03-091-29/+16
| | | | | | | | | | | | | clang-cl would warn that this value is not representable in 'int': enum { FeatureX = 1ULL << 31 }; All MS enums are 'ints' unless otherwise specified, so we have to use an explicit type. The AMDGPU target just hit 32 features, triggering this warning. Now that we have C++11 strong enum types, we can also eliminate the 'const uint64_t' codepath from tablegen and just use 'enum : uint64_t'. llvm-svn: 231697
* TableGen: Initialize ErrorInfo to ~0ULL in the MatchInstructionImplTom Stellard2015-03-051-1/+1
| | | | | | | | This is what all the targets check for and is consistent with the initialized value of MissingFeatures, which is sometimes assinged to ErrorInfo. llvm-svn: 231397
* Revert "[TableGen] Implement at least some support for multiple explicit ↵Craig Topper2015-03-051-10/+10
| | | | | | | | results in an instruction pattern. No functional change to existing patterns." This is failing on several build bots. llvm-svn: 231358
* [TableGen] Implement at least some support for multiple explicit results in ↵Craig Topper2015-03-051-10/+10
| | | | | | | | an instruction pattern. No functional change to existing patterns. This should help with the AVX512 masked gather changes Elena is working on. This patch is derived from some of the changes Elena made to tablegen, but modified by me to support arbitrary number of results. llvm-svn: 231357
* [TableGen] Add support constraining a vector type in a pattern to have a ↵Craig Topper2015-03-052-1/+126
| | | | | | specific element type and for constraining a vector type to have the same number of elements as another vector type. This is useful for AVX512 mask operations so we relate the mask type to the type of the other arguments. llvm-svn: 231356
* Add a FIXME for PR22796, broken ordering of ClassInfo in TableGenDavid Blaikie2015-03-041-0/+5
| | | | | | As discussed (at length) in code review of r222935, with Duncan. llvm-svn: 231282
* [Tablegen] Use correct result number variables with the pattern nodes they ↵Craig Topper2015-03-041-2/+2
| | | | | | go with when handling SDTCisSameAs. No functional change as they are always both 0 unless you try to define a multi result type profile that uses SDTCisSame on one of the other results. llvm-svn: 231226
* Revert "Remove the explicit SDNodeIterator::operator= in favor of the ↵David Blaikie2015-03-031-2/+0
| | | | | | | | | | | implicit default" Accidentally committed a few more of these cleanup changes than intended. Still breaking these out & tidying them up. This reverts commit r231135. llvm-svn: 231136
* Remove the explicit SDNodeIterator::operator= in favor of the implicit defaultDavid Blaikie2015-03-031-0/+2
| | | | | | | | | | There doesn't seem to be any need to assert that iterator assignment is between iterators over the same node - if you want to reuse an iterator variable to iterate another node, that's perfectly acceptable. Just don't mix comparisons between iterators into disjoint sequences, as usual. llvm-svn: 231135
* Switch up whitespace with better whitespace.Nick Lewycky2015-03-031-2/+2
| | | | llvm-svn: 231059
* Revert the non-cleanup part of r230769 because it introduced a ↵Nick Lewycky2015-03-032-3/+2
| | | | | | non-determinism found only in the names of symbols. llvm-svn: 231058
* TblGen: Remove copy of SmallVector::operator==. NFC intended.Benjamin Kramer2015-03-022-12/+3
| | | | llvm-svn: 230964
* Add missing includes. make_unique proliferated everywhere.Benjamin Kramer2015-03-011-0/+1
| | | | llvm-svn: 230909
* Reverted 230471 - gather scatter handling in table gen.Elena Demikhovsky2015-03-013-17/+5
| | | | llvm-svn: 230892
* AVX-512: Added mask and rounding mode for scalar arithmeticsElena Demikhovsky2015-03-011-0/+12
| | | | | | Added more tests for scalar instructions to destinguish between AVX and AVX-512 forms. llvm-svn: 230891
* Silence variable set but not used warning in CodeGenRegisters.cpp, NFC.Yaron Keren2015-02-281-0/+1
| | | | llvm-svn: 230854
* Replace std::copy with a back inserter with vector append where feasibleBenjamin Kramer2015-02-281-2/+3
| | | | | | | | | All of the cases were just appending from random access iterators to a vector. Using insert/append can grow the vector to the perfect size directly and moves the growing out of the loop. No intended functionalty change. llvm-svn: 230845
* Switch a std::map to a DenseMap in CodeGenRegisters.Owen Anderson2015-02-273-9/+12
| | | | | | | | The keys of the map are unique by pointer address, so there's no need to use the llvm::less comparator. This allows us to use DenseMap instead, which reduces tblgen time by 20% on my stress test. llvm-svn: 230769
* Re-instate the pragma optimize hack for MSVC, but not clang-clReid Kleckner2015-02-261-0/+8
| | | | | | Reverts commit r230686 with define modifications. llvm-svn: 230692
* Remove stale pragma hack for an unsupported MSVC versionReid Kleckner2015-02-261-8/+0
| | | | llvm-svn: 230686
* Fix a couple of depedent->dependent typos.Eric Christopher2015-02-261-1/+1
| | | | llvm-svn: 230584
* AVX-512: Gather and Scatter patternsElena Demikhovsky2015-02-253-5/+17
| | | | | | | | | | | | | | | Gather and scatter instructions additionally write to one of the source operands - mask register. In this case Gather has 2 destination values - the loaded value and the mask. Till now we did not support code gen pattern for gather - the instruction was generated from intrinsic only and machine node was hardcoded. When we introduce the masked_gather node, we need to select instruction automatically, in the standard way. I added a flag "hasTwoExplicitDefs" that allows to handle 2 destination operands. (Some code in the X86InstrFragmentsSIMD.td is commented out, just to split one big patch in many small patches) llvm-svn: 230471
* CodeGen: convert CCState interface to using ArrayRefsTim Northover2015-02-211-4/+3
| | | | | | | | | | | Everyone except R600 was manually passing the length of a static array at each callsite, calculated in a variety of interesting ways. Far easier to let ArrayRef handle that. There should be no functional change, but out of tree targets may have to tweak their calls as with these examples. llvm-svn: 230118
* Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein2015-02-194-50/+68
| | | | llvm-svn: 229841
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-02-194-68/+50
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
* MSVC 2013 does not ICE on this code in the same fashion that MSVC 2012 did; NFC.Aaron Ballman2015-02-161-3/+1
| | | | llvm-svn: 229422
* Removing LLVM_DELETED_FUNCTION, as MSVC 2012 was the last reason for ↵Aaron Ballman2015-02-151-2/+2
| | | | | | requiring the macro. NFC; LLVM edition. llvm-svn: 229340
* [X86] Add the remaining 11 possible exact ModRM formats. This makes their ↵Craig Topper2015-02-151-51/+62
| | | | | | encodings linear which can then be used to simplify some other code. llvm-svn: 229279
* [X86] Add support for parsing and printing the mnemonic aliases for the XOP ↵Craig Topper2015-02-131-0/+2
| | | | | | VPCOM instructions. llvm-svn: 229078
* MathExtras: Bring Count(Trailing|Leading)Ones and CountPopulation in line ↵Benjamin Kramer2015-02-121-2/+2
| | | | | | | | with countTrailingZeros Update all callers. llvm-svn: 228930
* Masked Gather and Scatter Intrinsics.Elena Demikhovsky2015-02-081-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Gather and Scatter are new introduced intrinsics, comming after recently implemented masked load and store. This is the first patch for Gather and Scatter intrinsics. It includes only the syntax, parsing and verification. Gather and Scatter intrinsics allow to perform multiple memory accesses (read/write) in one vector instruction. The intrinsics are not target specific and will have the following syntax: Gather: declare <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> <vector of ptrs>, i32 <alignment>, <16 x i1> <mask>, <16 x i32> <passthru>) declare <8 x float> @llvm.masked.gather.v8f32(<8 x float*><vector of ptrs>, i32 <alignment>, <8 x i1> <mask>, <8 x float><passthru>) Scatter: declare void @llvm.masked.scatter.v8i32(<8 x i32><vector value to be stored> , <8 x i32*><vector of ptrs> , i32 <alignment>, <8 x i1> <mask>) declare void @llvm.masked.scatter.v16i32(<16 x i32> <vector value to be stored> , <16 x i32*> <vector of ptrs>, i32 <alignment>, <16 x i1><mask> ) Vector of ptrs - a set of source/destination addresses, to load/store the value. Mask - switches on/off vector lanes to prevent memory access for switched-off lanes vector of ptrs, value and mask should have the same vector width. These are code examples where gather / scatter should be used and will allow function vectorization ;void foo1(int * restrict A, int * restrict B, int * restrict C) { ; for (int i=0; i<SIZE; i++) { ; A[i] = B[C[i]]; ; } ;} ;void foo3(int * restrict A, int * restrict B) { ; for (int i=0; i<SIZE; i++) { ; A[B[i]] = i+5; ; } ;} Tests will come in the following patches, with CodeGen and Vectorizer. http://reviews.llvm.org/D7433 llvm-svn: 228521
* STLExtras: Provide less/equal functors with templated function call ↵David Blaikie2015-02-023-43/+29
| | | | | | | | | | | | | | | | operators, plus a deref'ing functor template utility Similar to the C++14 void specializations of these templates, useful as a stop-gap until LLVM switches to '14. Example use-cases in tblgen because I saw some functors that looked like they could be simplified/refactored. Reviewers: dexonsmith Differential Revision: http://reviews.llvm.org/D7324 llvm-svn: 227828
* Replace another std::set in the core of CodeGenRegister, this time with ↵Owen Anderson2015-01-313-46/+61
| | | | | | | | sorted arrays. The hot path through this region of code does lots of batch inserts into sets. By storing them as sorted arrays, we can defer the sorting to the end of the batch, which is dramatically more efficient. This reduces tblgen runtime by 25% on my worst-case target. llvm-svn: 227682
* Change more of the guts of CodeGenRegister's RegUnit tracking to be based on ↵Owen Anderson2015-01-313-69/+45
| | | | | | | | bit vectors. This is a continuation of my prior work to move some of the inner workings for CodeGenRegister to use bit vectors when computing about register units. This is highly beneficial to TableGen runtime on targets with large, dense register files. This patch represents a ~40% runtime reduction over and above my earlier improvement on a stress test of this case. llvm-svn: 227678
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