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* Remove unncessary check for Int_* and *_Int in AsmMatcherEmitter. These are ↵Craig Topper2014-11-251-7/+0
| | | | | | all marked isCodeGenOnly these days. llvm-svn: 222783
* Use range-based for loops.Craig Topper2014-11-252-131/+90
| | | | llvm-svn: 222782
* Remove dead code.Craig Topper2014-11-253-7/+3
| | | | llvm-svn: 222781
* Remove unused MaxSize variable.Craig Topper2014-11-251-7/+0
| | | | llvm-svn: 222780
* Move a vector instead of copying it.Craig Topper2014-11-251-2/+2
| | | | llvm-svn: 222779
* Replace a comment that says 'unreachable' with llvm_unreachable in TableGen ↵Craig Topper2014-11-241-1/+1
| | | | | | AsmWriter output. llvm-svn: 222650
* Detect best type for some static index tables instead of just using uint32_t ↵Craig Topper2014-11-241-15/+24
| | | | | | to reduce total data size. llvm-svn: 222643
* Tablegen output formatting fixes.Craig Topper2014-11-231-2/+4
| | | | llvm-svn: 222633
* Masked Vector Load and Store Intrinsics.Elena Demikhovsky2014-11-232-2/+11
| | | | | | | | | | | | | | Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores. Added SDNodes for masked operations and lowering patterns for X86 code generator. Examples: <16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask) declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask) Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch. http://reviews.llvm.org/D6191 llvm-svn: 222632
* Reduce size of some tables in tablegen register info output.Craig Topper2014-11-222-50/+54
| | | | | | Primarily done by using SequenceToOffsetTable to reduce the register pressure set tables and then sizing the indices into the tables appropriately. Size a few other table entries based on content as well. Reduces X86RegisterInfo.o by ~9k. llvm-svn: 222621
* Add extra new line and remove some trailing whitespace from tablegen ↵Craig Topper2014-11-211-5/+5
| | | | | | RegisterInfo output file. llvm-svn: 222508
* Remove unnecessary extra spaces from tablegen register info output.Craig Topper2014-11-201-1/+1
| | | | llvm-svn: 222411
* Use array_lengthof instead of sizeof(array)/sizeof(element) in a tablegen ↵Craig Topper2014-11-201-5/+4
| | | | | | output. llvm-svn: 222410
* Update SetVector to rely on the underlying set's insert to return a ↵David Blaikie2014-11-192-4/+4
| | | | | | | | | | | | | pair<iterator, bool> This is to be consistent with StringSet and ultimately with the standard library's associative container insert function. This lead to updating SmallSet::insert to return pair<iterator, bool>, and then to update SmallPtrSet::insert to return pair<iterator, bool>, and then to update all the existing users of those functions... llvm-svn: 222334
* Remove StringMap::GetOrCreateValue in favor of StringMap::insertDavid Blaikie2014-11-191-3/+6
| | | | | | | | | | | | | | Having two ways to do this doesn't seem terribly helpful and consistently using the insert version (which we already has) seems like it'll make the code easier to understand to anyone working with standard data structures. (I also updated many references to the Entry's key and value to use first() and second instead of getKey{Data,Length,} and get/setValue - for similar consistency) Also removes the GetOrCreateValue functions so there's less surface area to StringMap to fix/improve/change/accommodate move semantics, etc. llvm-svn: 222319
* Make StringSet::insert return pair<iterator, bool> like other ↵David Blaikie2014-11-191-1/+1
| | | | | | | | | | | | self-associative containers StringSet is still a bit dodgy in that it exposes the raw iterator of the StringMap parent, which exposes the weird detail that StringSet actually has a 'value'... but anyway, this is useful for a handful of clients that want to reference the newly inserted/persistent string data in the StringSet/Map/Entry/thing. llvm-svn: 222302
* Revert "Improve memory ownership/management in TableGen by unique_ptrifying ↵David Blaikie2014-11-172-55/+47
| | | | | | | | | | | | TreePattern's Tree member." This reverts commit r222183. Broke on the MSVC buildbots due to MSVC not producing default move operations - I'd fix it immediately but just broke my build system a bit, so backing out until I have a chance to get everything going again. llvm-svn: 222187
* Improve memory ownership/management in TableGen by unique_ptrifying ↵David Blaikie2014-11-172-47/+55
| | | | | | | | | | | | TreePattern's Tree member. The next step is to actually use unique_ptr in TreePatternNode's Children vector. That will be more intrusive, and may not work, depending on exactly how these things are handled (I have a bad suspicion things are shared more than they should be, making this more DAG than tree - but if it's really a tree, unique_ptr should suffice) llvm-svn: 222183
* Move register class name strings to a single array in MCRegisterInfo to ↵Craig Topper2014-11-171-2/+14
| | | | | | | | reduce static table size and number of relocation entries. Indices into the table are stored in each MCRegisterClass instead of a pointer. A new method, getRegClassName, is added to MCRegisterInfo and TargetRegisterInfo to lookup the string in the table. llvm-svn: 222118
* Turn a leaked object into a stack variable instead.David Blaikie2014-11-141-19/+19
| | | | llvm-svn: 222046
* Change order of tablegen generated fast-isel instruction code to beBill Schmidt2014-11-141-105/+101
| | | | | | | | | | | | | | | | | | | | | based on instruction complexity The order that tablegen fast-isel instruction code is generated is currently based on the text of the predicate (using string less-than). This patch changes this to instead use the instruction complexity. Because the complexities are not unique a C++ multimap is used instead of a map. This fixes the problem where code with no predicate always comes out first (the empty string always compares as less than all other strings) thus making the code with predicates dead code. See the FMUL code in PPCFastISel.cpp for an example. It also more closely matches the normal codegen ordering. Some error checking in the tablegen fast-isel code is fixed as well. Patch by Bill Seurer. llvm-svn: 222038
* Fix nested namespace with decltype to hopefully work with MSVCDavid Blaikie2014-11-131-1/+2
| | | | | | | | | | Build failed here: http://lab.llvm.org:8011/builders/lld-x86_64-win7/builds/14629/steps/build_Lld/logs/stdio So I'm taking a shot in the dark that MSVC (whatever version that is) can't cope with nested name specifiers with a decltype prefix. llvm-svn: 221931
* Use unique_ptr to handle ownership of TreePatterns in ↵David Blaikie2014-11-133-23/+16
| | | | | | | | | CodeGenDAGPatterns::PatternFragments We might be able to use unique_ptr to handle ownership of the TreePatternNodes too - looking into that next. llvm-svn: 221928
* Make TreePattern::error use TwineMatt Arsenault2014-11-112-2/+2
| | | | | | | The underlying error function already uses a Twine, and most of the uses build up strings. llvm-svn: 221740
* MCAsmParserExtension has a copy of the MCAsmParser. Use it.Rafael Espindola2014-11-111-1/+1
| | | | | | Base classes were storing a second copy. llvm-svn: 221667
* Support REG_SEQUENCE in tablegen.Matt Arsenault2014-11-022-11/+63
| | | | | | | | | The problem is mostly that variadic output instruction aren't handled, so it is rejected for having an inconsistent number of operands, and then the right number of operands isn't emitted. llvm-svn: 221117
* Fix typoMatt Arsenault2014-11-021-1/+1
| | | | llvm-svn: 221116
* Fix missing C++ mode commentMatt Arsenault2014-11-021-1/+1
| | | | llvm-svn: 221115
* [tablegen] Add CustomCallingConv and use it to tablegen-erate the outermost ↵Daniel Sanders2014-11-011-14/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | parts of the Mips O32 implementation Summary: CustomCallingConv is simply a CallingConv that tablegen should not generate the implementation for. It allows regular CallingConv's to delegate to these custom functions. This is (currently) necessary for Mips and we cannot use CCCustom without having to adapt to the different API that CCCustom uses. This brings us a bit closer to being able to remove MipsCC::analyzeCallOperands and MipsCC::analyzeFormalArguments in favour of the common implementation. No functional change to the targets. Depends on D3341 Reviewers: vmedic Reviewed By: vmedic Subscribers: vmedic, llvm-commits Differential Revision: http://reviews.llvm.org/D5965 llvm-svn: 221052
* [AVX512] Extended avx512_sqrt_packed (sqrt instructions) to VL subset.Robert Khasanov2014-10-281-0/+5
| | | | | | Refactored through AVX512_maskable llvm-svn: 220806
* Moved out IIT_V64 from common values section.Robert Khasanov2014-10-201-5/+5
| | | | | | Thanks Juergen Ributzka for notice. llvm-svn: 220224
* [AVX512] Extended avx512_binop_rm for AVX512VL subsets.Robert Khasanov2014-10-091-0/+4
| | | | | | | Added avx512_binop_rm_vl multiclass for VL subset Added encoding tests llvm-svn: 219390
* [AVX512] Support mask register in MRMDestReg formatAdam Nemet2014-10-081-0/+2
| | | | | | This is necessary for masking vextract*x4. llvm-svn: 219359
* PR21101: tablegen's FastISel emitter should filter out unused functions.Bob Wilson2014-10-011-1/+16
| | | | | | | | | | | | | FastISel has a fixed set of virtual functions that are overridden by the tablegen-generated code for each target. These functions are distinguished by the kinds of operands, e.g., register + immediate = "ri". The FastISel emitter has been blindly emitting functions with different combinations of operand kinds, even for combinations that are completely unused by FastISel, e.g., "fastEmit_rrr". Change to filter out functions that will be irrelevant for FastISel and do not bother generating the code for them. Also add explicit "override" keywords for the virtual functions that are overridden. llvm-svn: 218838
* [X86 disasm tblegen backend] Clean up numPhysicalOperands assertsAdam Nemet2014-10-011-42/+35
| | | | | | | | | | | | | | No functionality change intended. This implements Elena's idea to put the new additionalOperand outside the switch to cover all cases (http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140929/237763.html). Note only nontrivial change is in MRMSrcMemFrm. This requires an inclusive interval of [2, 4] because we have prefix-dependent *optional* immediate operand. llvm-svn: 218790
* [AVX512] Added intrinsics for VPCMPEQB and VPCMPEQW.Robert Khasanov2014-09-301-18/+20
| | | | | | Added new operand type for intrinsics (IIT_V64) llvm-svn: 218668
* Reduce code duplication a bit.Craig Topper2014-09-271-16/+10
| | | | llvm-svn: 218563
* Fix TableGen -gen-disassembler output for bit fields with an offset.Craig Topper2014-09-271-1/+5
| | | | | | | | | This fixes bit assignments like this Inst{7-0} = Foo{9-2} Patch by Steve King. llvm-svn: 218560
* [mips] Add CCValAssign::[ASZ]ExtUpper and CCPromoteToUpperBitsInType and ↵Daniel Sanders2014-09-251-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | handle struct's correctly on big-endian N32/N64 return values. Summary: The N32/N64 ABI's require that structs passed in registers are laid out such that spilling the register with 'sd' places the struct at the lowest address. For little endian this is trivial but for big-endian it requires that structs are shifted into the upper bits of the register. We also require that structs passed in registers have the 'inreg' attribute for big-endian N32/N64 to work correctly. This is because the tablegen-erated calling convention implementation only has access to the lowered form of struct arguments (one or more integers of up to 64-bits each) and is unable to determine the original type. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5286 llvm-svn: 218451
* [x86] Fix a pretty horrible bug and inconsistency in the x86 asmChandler Carruth2014-09-061-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | parsing (and latent bug in the instruction definitions). This is effectively a revert of r136287 which tried to address a specific and narrow case of immediate operands failing to be accepted by x86 instructions with a pretty heavy hammer: it introduced a new kind of operand that behaved differently. All of that is removed with this commit, but the test cases are both preserved and enhanced. The core problem that r136287 and this commit are trying to handle is that gas accepts both of the following instructions: insertps $192, %xmm0, %xmm1 insertps $-64, %xmm0, %xmm1 These will encode to the same byte sequence, with the immediate occupying an 8-bit entry. The first form was fixed by r136287 but that broke the prior handling of the second form! =[ Ironically, we would still emit the second form in some cases and then be unable to re-assemble the output. The reason why the first instruction failed to be handled is because prior to r136287 the operands ere marked 'i32i8imm' which forces them to be sign-extenable. Clearly, that won't work for 192 in a single byte. However, making thim zero-extended or "unsigned" doesn't really address the core issue either because it breaks negative immediates. The correct fix is to make these operands 'i8imm' reflecting that they can be either signed or unsigned but must be 8-bit immediates. This patch backs out r136287 and then changes those places as well as some others to use 'i8imm' rather than one of the extended variants. Naturally, this broke something else. The custom DAG nodes had to be updated to have a much more accurate type constraint of an i8 node, and a bunch of Pat immediates needed to be specified as i8 values. The fallout didn't end there though. We also then ceased to be able to match the instruction-specific intrinsics to the instructions so modified. Digging, this is because they too used i32 rather than i8 in their signature. So I've also switched those intrinsics to i8 arguments in line with the instructions. In order to make the intrinsic adjustments of course, I also had to add auto upgrading for the intrinsics. I suspect that the intrinsic argument types may have led everything down this rabbit hole. Pretty happy with the result. llvm-svn: 217310
* Use vector constructor instead of a for loop to initialize entries.Craig Topper2014-09-041-4/+2
| | | | llvm-svn: 217123
* [FastISel][tblgen] Rename tblgen generated FastISel functions. NFC.Juergen Ributzka2014-09-031-12/+12
| | | | | | | | | | This is the final round of renaming. This changes tblgen to emit lower-case function names for FastEmitInst_* and FastEmit_*, and updates all its uses in the source code. Reviewed by Eric llvm-svn: 217075
* Fix ambiguous call to make_unique and clang-format.Yaron Keren2014-09-031-13/+7
| | | | llvm-svn: 217023
* Recommit "Use unique_ptr to manager FilterChooser ownership."Craig Topper2014-09-031-23/+16
| | | | | | Just using insert of a pair this time instead of emplace. llvm-svn: 217018
* Revert "Use unique_ptr to manager FilterChooser ownership."Craig Topper2014-09-031-15/+24
| | | | | | std::map::emplace isn't working on some of the bots. llvm-svn: 217015
* Use unique_ptr to manager FilterChooser ownership.Craig Topper2014-09-031-24/+15
| | | | llvm-svn: 217014
* Implement move constructor and remove copy constructor for Filter objects in ↵Craig Topper2014-09-031-13/+8
| | | | | | FixedLenDecoderEmitter. Also remove unused copy constructor of FilterChooser. llvm-svn: 217013
* Tablegen scheduling models don't reference empty itineraries as of r216919, ↵Pete Cooper2014-09-021-4/+5
| | | | | | so don't emit the unused itinerary variables llvm-svn: 216993
* Reinstate "Nuke the old JIT."Eric Christopher2014-09-021-20/+6
| | | | | | | | Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 216982
* Change MCSchedModel to be a struct of statically initialized data.Pete Cooper2014-09-021-4/+4
| | | | | | | | This removes static initializers from the backends which generate this data, and also makes this struct match the other Tablegen generated structs in behaviour Reviewed by Andy Trick and Chandler C llvm-svn: 216919
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