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* Fix typos in comments, NFCRobin Morisset2014-08-291-1/+1
| | | | | | | | | | | | | | Summary: Just fixing comments, no functional change. Test Plan: N/A Reviewers: jfb Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D5130 llvm-svn: 216784
* Simplify creation of a bunch of ArrayRefs by using None, makeArrayRef or ↵Craig Topper2014-08-271-2/+1
| | | | | | just letting them be implicitly created. llvm-svn: 216525
* Fix some cases were ArrayRefs were being passed by reference. Also remove ↵Craig Topper2014-08-271-1/+1
| | | | | | 'const' from some other ArrayRef uses since its implicitly const already. llvm-svn: 216524
* [SKX] avx512_icmp_packed multiclass extensionRobert Khasanov2014-08-252-0/+8
| | | | | | | | | | | | | Extended avx512_icmp_packed multiclass by masking versions. Added avx512_icmp_packed_rmb multiclass for embedded broadcast versions. Added corresponding _vl multiclasses. Added encoding tests for CPCMP{EQ|GT}* instructions. Add more fields for X86VectorVTInfo. Added AVX512VLVectorVTInfo that include X86VectorVTInfo for 512/256/128-bit versions Differential Revision: http://reviews.llvm.org/D5024 llvm-svn: 216383
* Use range based for loops to avoid needing to re-mention SmallPtrSet size.Craig Topper2014-08-241-3/+2
| | | | llvm-svn: 216351
* TableGen: unique_ptr-ify RecordKeeperDylan Noblesmith2014-08-242-3/+3
| | | | llvm-svn: 216350
* TableGen: use auto and for-rangeDylan Noblesmith2014-08-242-15/+10
| | | | llvm-svn: 216348
* Repace SmallPtrSet with SmallPtrSetImpl in function arguments to avoid ↵Craig Topper2014-08-211-6/+6
| | | | | | needing to mention the size. llvm-svn: 216158
* Add isInsertSubreg property.Quentin Colombet2014-08-203-0/+3
| | | | | | | | | | | | | This patch adds a new property: isInsertSubreg and the related target hooks: TargetIntrInfo::getInsertSubregInputs and TargetInstrInfo::getInsertSubregLikeInputs to specify that a target specific instruction is a (kind of) INSERT_SUBREG. The approach is similar to r215394. <rdar://problem/12702965> llvm-svn: 216139
* Add isExtractSubreg property.Quentin Colombet2014-08-203-0/+3
| | | | | | | | | | | | | This patch adds a new property: isExtractSubreg and the related target hooks: TargetIntrInfo::getExtractSubregInputs and TargetInstrInfo::getExtractSubregLikeInputs to specify that a target specific instruction is a (kind of) EXTRACT_SUBREG. The approach is similar to r215394. <rdar://problem/12702965> llvm-svn: 216130
* TableGen: allow use of uint64_t for available features mask.Tim Northover2014-08-181-19/+21
| | | | | | | | | | ARM in particular is getting dangerously close to exceeding 32 bits worth of possible subtarget features. When this happens, various parts of MC start to fail inexplicably as masks get truncated to "unsigned". Mostly just refactoring at present, and there's probably no way to test. llvm-svn: 215887
* Revert "Repace SmallPtrSet with SmallPtrSetImpl in function arguments to ↵Craig Topper2014-08-181-6/+6
| | | | | | | | avoid needing to mention the size." Getting a weird buildbot failure that I need to investigate. llvm-svn: 215870
* Repace SmallPtrSet with SmallPtrSetImpl in function arguments to avoid ↵Craig Topper2014-08-171-6/+6
| | | | | | needing to mention the size. llvm-svn: 215868
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-1314-26/+30
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Add isRegSequence property.Quentin Colombet2014-08-113-0/+3
| | | | | | | | | | | This patch adds a new property: isRegSequence and the related target hooks: TargetIntrInfo::getRegSequenceInputs and TargetInstrInfo::getRegSequenceLikeInputs to specify that a target specific instruction is a (kind of) REG_SEQUENCE. <rdar://problem/12702965> llvm-svn: 215394
* Temporarily Revert "Nuke the old JIT." as it's not quite ready toEric Christopher2014-08-071-6/+20
| | | | | | | | | | | be deleted. This will be reapplied as soon as possible and before the 3.6 branch date at any rate. Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reverts commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 215154
* Nuke the old JIT.Rafael Espindola2014-08-071-20/+6
| | | | | | | | | I am sure we will be finding bits and pieces of dead code for years to come, but this is a good start. Thanks to Lang Hames for making MCJIT a good replacement! llvm-svn: 215111
* Change BitsInit to inherit from TypedInit.Pete Cooper2014-08-071-0/+15
| | | | | | This is useful in a later patch where binary literals such as 0b000 will become BitsInit values instead of IntInit values. llvm-svn: 215085
* Remove the target machine from CCState. Previously it was only usedEric Christopher2014-08-061-2/+2
| | | | | | | | | to get the subtarget and that's accessible from the MachineFunction now. This helps clear the way for smaller changes where we getting a subtarget will require passing in a MachineFunction/Function as well. llvm-svn: 214988
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-4/+8
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* [SKX] Enabling load/store instructions: encodingRobert Khasanov2014-08-041-0/+11
| | | | | | | | Instructions: VMOVAPD, VMOVAPS, VMOVDQA8, VMOVDQA16, VMOVDQA32,VMOVDQA64, VMOVDQU8, VMOVDQU16, VMOVDQU32,VMOVDQU64, VMOVUPD, VMOVUPS, Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 214719
* Make getNamedOperandIdx readonlyMatt Arsenault2014-08-011-0/+1
| | | | llvm-svn: 214524
* TableGen: Allow AddedComplexity values to be negativeTom Stellard2014-08-013-7/+7
| | | | | | | | | | | | | This is useful for cases when stand-alone patterns are preferred to the patterns included in the instruction definitions. Instead of requiring that stand-alone patterns set a larger AddedComplexity value, which can be confusing to new developers, the allows us to reduce the complexity of the included patterns to achieve the same result. There will be test cases for this added to the R600 backend in a future commit. llvm-svn: 214466
* Add support for the X86 secure guard extensions instructions in assembler (SGX).Kevin Enderby2014-07-311-56/+59
| | | | | | | | | | | | | This allows assembling the two new instructions, encls and enclu for the SKX processor model. Note the diffs are a bigger than what might think, but to fit the new MRM_CF and MRM_D7 in things in the right places things had to be renumbered and shuffled down causing a bit more diffs. rdar://16228228 llvm-svn: 214460
* [SKX] Enabling mask logic instructions: encoding, loweringRobert Khasanov2014-07-281-0/+2
| | | | | | | | Instructions: KAND{BWDQ}, KANDN{BWDQ}, KOR{BWDQ}, KXOR{BWDQ}, KXNOR{BWDQ} Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 214081
* [stack protector] Fix a potential security bug in stack protector where theAkira Hatanaka2014-07-251-1/+2
| | | | | | | | | | | | | | address of the stack guard was being spilled to the stack. Previously the address of the stack guard would get spilled to the stack if it was impossible to keep it in a register. This patch introduces a new target independent node and pseudo instruction which gets expanded post-RA to a sequence of instructions that load the stack guard value. Register allocator can now just remat the value when it can't keep it in a register. <rdar://problem/12475629> llvm-svn: 213967
* [SKX] Enabling mask instructions: encoding, loweringRobert Khasanov2014-07-231-0/+4
| | | | | | | | KMOVB, KMOVW, KMOVD, KMOVQ, KNOTB, KNOTW, KNOTD, KNOTQ Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 213757
* Revert of r213521. This change introduced a non-hermetic test (depending on aRichard Smith2014-07-223-7/+7
| | | | | | | | | | file not in the test/ area). Backing out now so that this test isn't part of the 3.5 branch. Original commit message: "TableGen: Allow AddedComplexity values to be negative [...]" llvm-svn: 213596
* [SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features.Robert Khasanov2014-07-211-0/+14
| | | | | | | | | | | | Enabling HasAVX512{DQ,BW,VL} predicates. Adding VK2, VK4, VK32, VK64 masked register classes. Adding new types (v64i8, v32i16) to VR512. Extending calling conventions for new types (v64i8, v32i16) Patch by Zinovy Nis <zinovy.y.nis@intel.com> Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 213545
* TableGen: Allow AddedComplexity values to be negativeTom Stellard2014-07-213-7/+7
| | | | | | | | | | This is useful for cases when stand-alone patterns are preferred to the patterns included in the instruction definitions. Instead of requiring that stand-alone patterns set a larger AddedComplexity value, which can be confusing to new developers, the allows us to reduce the complexity of the included patterns to achieve the same result. llvm-svn: 213521
* Remove uses of the redundant ".reset(nullptr)" of unique_ptr, in favor of ↵David Blaikie2014-07-191-1/+1
| | | | | | | | | | | ".reset()" It's also possible to just write "= nullptr", but there's some question of whether that's as readable, so I leave it up to authors to pick which they prefer for now. If we want to discuss standardizing on one or the other, we can do that at some point in the future. llvm-svn: 213438
* TableGen: Add 'static' to a large array to avoid a huge stack allocationReid Kleckner2014-07-171-1/+1
| | | | | | | | Speculative fix for a -Wframe-larger-than warning from gcc. Clang will implicitly promote such constant arrays to globals, so in theory it won't hit this. llvm-svn: 213298
* [X86] AVX512: Add disassembler support for compressed displacementAdam Nemet2014-07-172-2/+20
| | | | | | | | | | | | There are two parts here. First is to modify tablegen to adjust the encoding type ENCODING_RM with the scaling factor. The second is to use the new encoding types to compute the correct displacement in the decoder. Fixes <rdar://problem/17608489> llvm-svn: 213281
* [TABLEGEN] Do not crash on intrinsics with names longer than 40 charactersJustin Holewinski2014-07-171-2/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D4537 llvm-svn: 213253
* Move Post RA Scheduling flag bit into SchedMachineModelSanjay Patel2014-07-151-0/+4
| | | | | | | | | | | | | | | | | | | | | Refactoring; no functional changes intended Removed PostRAScheduler bits from subtargets (X86, ARM). Added PostRAScheduler bit to MCSchedModel class. This bit is set by a CPU's scheduling model (if it exists). Removed enablePostRAScheduler() function from TargetSubtargetInfo and subclasses. Fixed the existing enablePostMachineScheduler() method to use the MCSchedModel (was just returning false!). Added methods to TargetSubtargetInfo to allow overrides for AntiDepBreakMode, CriticalPathRCs, and OptLevel for PostRAScheduling. Added enablePostRAScheduler() function to PostRAScheduler class which queries the subtarget for the above values. Preserved existing scheduler behavior for ARM, MIPS, PPC, and X86: a. ARM overrides the CPU's postRA settings by enabling postRA for any non-Thumb or Thumb2 subtarget. b. MIPS overrides the CPU's postRA settings by enabling postRA for everything. c. PPC overrides the CPU's postRA settings by enabling postRA for everything. d. X86 is the only target that actually has postRA specified via sched model info. Differential Revision: http://reviews.llvm.org/D4217 llvm-svn: 213101
* Option: Propagate flags from groups to options in each groupReid Kleckner2014-07-121-11/+15
| | | | | | | This should make it easy to set a flag for a whole group of clang driver options. llvm-svn: 212865
* Change an assert() to a diagnostic.Jim Grosbach2014-07-091-3/+5
| | | | llvm-svn: 212637
* SourceMgr: make valid buffer IDs start from oneAlp Toker2014-07-061-2/+2
| | | | | | | | | | Use 0 for the invalid buffer instead of -1/~0 and switch to unsigned representation to enable more idiomatic usage. Also introduce a trivial SourceMgr::getMainFileID() instead of hard-coding 0/1 to identify the main file. llvm-svn: 212398
* TableGen: introduce support for MSBuiltinSaleem Abdulrasool2014-07-043-0/+57
| | | | | | | | | | | | | Add MSBuiltin which is similar in vein to GCCBuiltin. This allows for adding intrinsics for Microsoft compatibility to individual instructions. This is needed to permit the creation of ARM specific MSVC extensions. This is not currently in use, and requires an associated change in clang to enable use of the intrinsics defined by this new class. This merely sets the LLVM portion of the infrastructure in place to permit the use of this functionality. A separate set of changes will enable the new intrinsics. llvm-svn: 212350
* Revert "Introduce a string_ostream string builder facilty"Alp Toker2014-06-261-1/+2
| | | | | | Temporarily back out commits r211749, r211752 and r211754. llvm-svn: 211814
* Introduce a string_ostream string builder faciltyAlp Toker2014-06-261-2/+1
| | | | | | | | | | | | | | | | | | | | string_ostream is a safe and efficient string builder that combines opaque stack storage with a built-in ostream interface. small_string_ostream<bytes> additionally permits an explicit stack storage size other than the default 128 bytes to be provided. Beyond that, storage is transferred to the heap. This convenient class can be used in most places an std::string+raw_string_ostream pair or SmallString<>+raw_svector_ostream pair would previously have been used, in order to guarantee consistent access without byte truncation. The patch also converts much of LLVM to use the new facility. These changes include several probable bug fixes for truncated output, a programming error that's no longer possible with the new interface. llvm-svn: 211749
* Use SourceMgr::getMemoryBuffer() in a couple of placesAlp Toker2014-06-251-1/+1
| | | | | | Cleanup only. llvm-svn: 211656
* Replace some assert(0)'s with llvm_unreachable.Craig Topper2014-06-181-1/+1
| | | | llvm-svn: 211141
* Move SetTheory from utils/TableGen into lib/TableGen so Clang can use it.James Molloy2014-06-176-469/+3
| | | | llvm-svn: 211100
* Condition codes AL and NV are invalid in the aliases that useArtyom Skrobov2014-06-101-3/+46
| | | | | | | | | | | | | | inverted condition codes (CINC, CINV, CNEG, CSET, and CSETM). Matching aliases based on "immediate classes", when disassembling, wasn't previously supported, hence adding MCOperandPredicate into class Operand, and implementing the support for it in AsmWriterEmitter. The parsing for those aliases was already custom, so just adding the missing condition into AArch64AsmParser::parseCondCode. llvm-svn: 210528
* Refactoring in AsmWriterEmitter::EmitPrintAliasInstruction()Artyom Skrobov2014-06-101-11/+6
| | | | llvm-svn: 210527
* AsmMatchers: Use unique_ptr to manage ownership of MCParsedAsmOperandDavid Blaikie2014-06-081-24/+23
| | | | | | | | | | | | I saw at least a memory leak or two from inspection (on probably untested error paths) and r206991, which was the original inspiration for this change. I ran this idea by Jim Grosbach a few weeks ago & he was OK with it. Since it's a basically mechanical patch that seemed sufficient - usual post-commit review, revert, etc, as needed. llvm-svn: 210427
* Teach the table generated emitPseudoExpansionLowering function to not emit a ↵Aaron Ballman2014-05-231-61/+65
| | | | | | switch statement containing only a default statement (and no cases). Updated some of the code to use range-based for loops as well. No functional changes. llvm-svn: 209521
* ARM64: separate load/store operands to simplify assemblerTim Northover2014-05-221-3/+3
| | | | | | | | | | | | | | | | | | | This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
* [asm matcher] Fix incorrect assertion when there are exactly 32 ↵Daniel Sanders2014-05-211-13/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | SubtargetFeatures Summary: The minimal type needs to hold a value of '1ULL << 31' but getMinimalTypeForRange() is called with a value of '1ULL << 32'. This patch will also reduce the size of the matcher table when there are 8 or 16 SubtargetFeatures. Also added a dump of the SubtargetFeatures to the -debug output and corrected getMinimalTypeInRange() to consider 0xffffffffull to be a 32-bit value. The testcase is that no existing code is broken and that LLVM still successfully compiles after adding MIPS64r6 CodeGen support. Reviewers: rafael Reviewed By: rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3787 llvm-svn: 209288
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