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* tblgen: Assert that InstRWs doesn't grows when we don't expect it.Benjamin Kramer2013-06-101-0/+1
| | | | llvm-svn: 183690
* tblgen: always lookup values from the original vector as it could be grown ↵Benjamin Kramer2013-06-091-6/+6
| | | | | | | | under our feet. PR16281. llvm-svn: 183630
* CodeGenSchedule: Use resize instead of copying a vectorArnold Schwaighofer2013-06-071-2/+2
| | | | llvm-svn: 183465
* CodeGenSchedule: smallvector.push_back(smallvector[0]) is dangerousArnold Schwaighofer2013-06-061-1/+3
| | | | | | | | | | The element passed to push_back is not copied before the vector reallocates. The client needs to copy the element first before passing it to push_back. No test case, will be tested by follow-up swift scheduler model change (it segfaults without this change). llvm-svn: 183459
* Remove unimplemented definition. Found using [-Wunused-member-function].Jakub Staszak2013-06-061-2/+0
| | | | llvm-svn: 183426
* SubtargetEmitter fixArnold Schwaighofer2013-06-051-1/+1
| | | | | | | | | Don't output data if we are supposed to ignore the record. Reapply of 183255, I don't think this was causing the tablegen segfault on linux testers. llvm-svn: 183311
* Fix a tblgen subtargetemitter bug, for future Swift support.Andrew Trick2013-06-051-4/+23
| | | | | | | | | | This fixes some of the ridiculously complex code for optimizing the machine model tables that are shared among all processors of a given target. A9 and Swift both use the "special" feature that maps old itinerary classes to new machine model defs. They map different overlapping subsets of instructions, which wasn't handled correctly. llvm-svn: 183302
* Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer2013-06-041-1/+1
| | | | llvm-svn: 183273
* SubtargetEmitter fixArnold Schwaighofer2013-06-041-1/+1
| | | | | | Don't output data if we are supposed to ignore the record. llvm-svn: 183255
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-313-7/+18
| | | | | | | This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. llvm-svn: 183061
* Add a way to define the bit range covered by a SubRegIndex.Ahmed Bougacha2013-05-313-5/+36
| | | | | | | | | | | | | NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change the instances of SubRegIndex that have a comps template arg to use the ComposedSubRegIndex class instead. In TableGen land, this adds Size and Offset attributes to SubRegIndex, and the ComposedSubRegIndex class, for which the Size and Offset are computed by TableGen. This also adds an accessor in MCRegisterInfo, and Size/Offsets for the X86 and ARM subreg indices. llvm-svn: 183020
* Remove the MCRegAliasIterator tables and compute the aliases dynamically.Chad Rosier2013-05-283-66/+3
| | | | | | | | | | | | | | | | | | | | The size reduction in the RegDiffLists are rather dramatic. Here are a few size differences for MCTargetDesc.o files (before and after) in bytes: R600 - 36160B - 11184B - 69% reduction ARM - 28480B - 8368B - 71% reduction Mips - 816B - 576B - 29% reduction One side effect of dynamically computing the aliases is that the iterator does not guarantee that the entries are ordered or that duplicates have been removed. The documentation implies this is a safe assumption and I found no clients that requires these attributes (i.e., strict ordering and uniqueness). My local LNT tester results showed no execution-time failures or significant compile-time regressions (i.e., beyond what I would consider noise) for -O0g, -O2 and -O3 runs on x86_64 and i386 configurations. rdar://12906217 llvm-svn: 182783
* Recognize ValueType operands in source patterns for fast-isel.Bill Schmidt2013-05-221-3/+7
| | | | | | | | | | | | | | | | | | | | | Currently the fast-isel table generator recognizes registers, register classes, and immediates for source pattern operands. ValueType operands are not recognized. This is not a problem for existing targets with fast-isel support, but will not work for targets like PowerPC and SPARC that use types in source patterns. The proposed patch allows ValueType operands and treats them in the same manner as register classes. There is no convenient way to map from a ValueType to a register class, but there's no need to do so. The table generator already requires that all types in the source pattern be identical, and we know the register class of the output operand already. So we just assign that register class to any ValueType operands we encounter. No functional effect on existing targets. Testing deferred until the PowerPC target implements fast-isel. llvm-svn: 182512
* Add TargetRegisterInfo::getCoveringLanes().Jakob Stoklund Olesen2013-05-163-6/+35
| | | | | | | | This lane mask provides information about which register lanes completely cover super-registers. See the block comment before getCoveringLanes(). llvm-svn: 182034
* Handle tied sub-operands in AsmMatcherEmitterUlrich Weigand2013-04-271-30/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The problem this patch addresses is the handling of register tie constraints in AsmMatcherEmitter, where one operand is tied to a sub-operand of another operand. The typical scenario for this to happen is the tie between the "write-back" register of a pre-inc instruction, and the base register sub-operand of the memory address operand of that instruction. The current AsmMatcherEmitter code attempts to handle tied operands by emitting the operand as usual first, and emitting a CVT_Tied node when handling the second (tied) operand. However, this really only works correctly if the tied operand does not have sub-operands (and isn't a sub-operand itself). Under those circumstances, a wrong MC operand list is generated. In discussions with Jim Grosbach, it turned out that the MC operand list really ought not to contain tied operands in the first place; instead, it ought to consist of exactly those operands that are named in the AsmString. However, getting there requires significant rework of (some) targets. This patch fixes the immediate problem, and at the same time makes one (small) step in the direction of the long-term solution, by implementing two changes: 1. Restricts the AsmMatcherEmitter handling of tied operands to apply solely to simple operands (not complex operands or sub-operand of such). This means that at least we don't get silently corrupt MC operand lists as output. However, if we do have tied sub-operands, they would now no longer be handled at all, except for: 2. If we have an operand that does not occur in the AsmString, and also isn't handled as tied operand, simply emit a dummy MC operand (constant 0). This works as long as target code never attempts to access MC operands that do no not occur in the AsmString (and are not tied simple operands), which happens to be the case for all targets where this situation can occur (ARM and PowerPC). [ Note that this change means that many of the ARM custom converters are now superfluous, since the implement the same "hack" now performed already by common code. ] Longer term, we ought to fix targets to never access *any* MC operand that does not occur in the AsmString (including tied simple operands), and then finally completely remove all such operands from the MC operand list. Patch approved by Jim Grosbach. llvm-svn: 180677
* Machine model: Generate table entries for super-resources.Andrew Trick2013-04-231-14/+23
| | | | | | | | | Super-resources and resource groups are two ways of expressing overlapping sets of processor resources. Now we generate table entries the same way for both so the scheduler never needs to explicitly check for super-resources. llvm-svn: 180162
* Machine model: verify well-formed processor resource groups.Andrew Trick2013-04-232-0/+54
| | | | llvm-svn: 180161
* Machine model: rewrite a tablegen loop to avoid comparing record pointers.Andrew Trick2013-04-231-8/+4
| | | | llvm-svn: 180160
* [asm parser] Add support for predicating MnemonicAlias based on the assemblerChad Rosier2013-04-181-20/+45
| | | | | | | | variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. llvm-svn: 179804
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-111-17/+19
| | | | | | | As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. llvm-svn: 179266
* Fix TableGen subtarget-emitter to handle A9/Swift.Andrew Trick2013-03-291-5/+11
| | | | | | | | A9 uses itinerary classes, Swift uses RW lists. This tripped some verification when we're expanding variants. I had to refine the verification a bit. llvm-svn: 178357
* Revert r178166. According to Howard, this code is actually ok.Dan Gohman2013-03-291-3/+1
| | | | llvm-svn: 178319
* Avoid undefined behavior from passing a std::vector's own contentsDan Gohman2013-03-271-1/+3
| | | | | | in as an argument to push_back. llvm-svn: 178166
* TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.Andrew Trick2013-03-262-2/+24
| | | | | | Allow variants to be defined only for some processors on a target. llvm-svn: 178074
* x86 -- add the XTEST instructionDave Zarzycki2013-03-251-8/+9
| | | | llvm-svn: 177888
* Allow types to be omitted in output patterns.Jakob Stoklund Olesen2013-03-242-0/+16
| | | | | | | | | | This syntax is now preferred: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; There is no reason to repeat the types in the output pattern. llvm-svn: 177844
* Allow direct value types to be used in instruction 'set' patterns.Jakob Stoklund Olesen2013-03-241-2/+24
| | | | | | | | | | | | This makes it possible to define instruction patterns like this: def LDri : F3_2<3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr), "ld [$addr], $dst", [(set i32:$dst, (load ADDRri:$addr))]>; ~~~ llvm-svn: 177834
* Allow direct value types in pattern definitions.Jakob Stoklund Olesen2013-03-232-5/+29
| | | | | | | | | | | | | | | | | Just like register classes, value types can be used in two ways in patterns: (sext_inreg i32:$src, i16) In a named leaf node like i32:$src, the value type simply provides the type of the node directly. This simplifies type inference a lot compared to the current practice of specifiying types indirectly with register classes. As an unnamed leaf node, like i16 above, the value type represents itself as an MVT::Other immediate. llvm-svn: 177828
* Make all unnamed RegisterClass TreePatternNodes typed MVT::i32.Jakob Stoklund Olesen2013-03-232-21/+21
| | | | | | | | | | | | | | | | | | | | | A register class can appear as a leaf TreePatternNode with and without a name: (COPY_TO_REGCLASS GPR:$src, F8RC) In a named leaf node like GPR:$src, the register class provides type information for the named variable represented by the node. The TypeSet for such a node is the set of value types that the register class can represent. In an unnamed leaf node like F8RC above, the register class represents itself as a kind of immediate. Such a node has the type MVT::i32, we'll never create a virtual register representing it. This change makes it possible to remove the special handling of COPY_TO_REGCLASS in CodeGenDAGPatterns.cpp. llvm-svn: 177825
* Add TableGen ctags(1) emitter and helper script.Sean Silva2013-03-215-1/+561
| | | | | | | | | | | | | | | | | | | | | To use this in conjunction with exuberant ctags to generate a single combined tags file, run tblgen first and then $ ctags --append [...] Since some identifiers have corresponding definitions in C++ code, it can be useful (if using vim) to also use cscope, and :set cscopetagorder=1 so that :tag X will preferentially select the tablegen symbol, while :cscope find g X will always find the C++ symbol. Patch by Kevin Schoedel! (a couple small formatting changes courtesy of clang-format) llvm-svn: 177682
* Extend TableGen instruction selection matcher to improve handlingUlrich Weigand2013-03-192-11/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of complex instruction operands (e.g. address modes). Currently, if a Pat pattern creates an instruction that has a complex operand (i.e. one that consists of multiple sub-operands at the MI level), this operand must match a ComplexPattern DAG pattern with the correct number of output operands. This commit extends TableGen to alternatively allow match a complex operands against multiple separate operands at the DAG level. This allows using Pat patterns to match pre-increment nodes like pre_store (which must have separate operands at the DAG level) onto an instruction pattern that uses a multi-operand memory operand, like the following example on PowerPC (will be committed as a follow-on patch): def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst), "stwu $rS, $dst", LdStStoreUpd, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff), (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>; Here, the pair of "ptroff" and "ptrreg" operands is matched onto the complex operand "dst" of class "memri" in the "STWU" instruction. Approved by Jakob Stoklund Olesen. llvm-svn: 177428
* TableGen fix for the new machine model.Andrew Trick2013-03-181-4/+6
| | | | | | | | Properly handle cases where a group of instructions have different SchedRW lists with the same itinerary class. This was supposed to work, but I left in an early break. llvm-svn: 177317
* Extract a method.Jakob Stoklund Olesen2013-03-182-41/+42
| | | | | | | This computes the type of an instruction operand or result based on the records in the instruction's ins and outs lists. llvm-svn: 177244
* Use ArrayRef<MVT::SimpleValueType> when possible.Jakob Stoklund Olesen2013-03-176-10/+10
| | | | | | | Not passing vector references around makes it possible to use SmallVector in most places. llvm-svn: 177235
* Machine model. Allow mixed itinerary classes and SchedRW lists.Andrew Trick2013-03-163-205/+174
| | | | | | | | | | | | | We always supported a mixture of the old itinerary model and new per-operand model, but it required a level of indirection to map itinerary classes to SchedRW lists. This was done for ARM A9. Now we want to define x86 SchedRW lists, with the goal of removing its itinerary classes, but still support the itineraries in the mean time. When I original developed the model, Atom did not have itineraries, so there was no reason to expect this requirement. llvm-svn: 177226
* Add SchedRW as an Instruction field.Jakob Stoklund Olesen2013-03-151-6/+6
| | | | | | | | | | | | | Don't require instructions to inherit Sched<...>. Sometimes it is more convenient to say: let SchedRW = ... in { ... } Which is now possible. llvm-svn: 177199
* Fix r177112: Add ProcResGroup.Andrew Trick2013-03-141-1/+3
| | | | | | This is the other half of r177122 that I meant to commit at the same time. llvm-svn: 177123
* MachineModel: Add a ProcResGroup class.Andrew Trick2013-03-142-12/+92
| | | | | | | | | | | | | | | | | This allows abitrary groups of processor resources. Using something in a subset automatically counts againts the superset. Currently, this only works if the superset is also a ProcResGroup as opposed to a SuperUnit. This allows SandyBridge to be expressed naturally, which will be checked in shortly. def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; def SBPort23 : ProcResGroup<[SBPort2, SBPort3]>; def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; llvm-svn: 177112
* Fixes disassembler crashes on 2013 Haswell RTM instructions.Kevin Enderby2013-03-111-0/+11
| | | | | | rdar://13318048 llvm-svn: 176828
* MIsched machine model: tablegen subtarget emitter improvement.Andrew Trick2013-03-011-1/+14
| | | | | | | | Fix the way resources are counted. I'm taking some time to cleanup the way MachineScheduler handles in-order machine resources. Eventually we'll need more PPC/Atom test cases in tree. llvm-svn: 176390
* [TableGen] Fix ICE on MSVC 2012 Release builds.Michael J. Spencer2013-02-261-1/+3
| | | | llvm-svn: 176125
* Fix for bug 15246 -- out-of-bound error in the TableGen backend, ↵Jyotsna Verma2013-02-141-5/+4
| | | | | | CodeGenMapTable.cpp. llvm-svn: 175185
* PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIADavid Peixotto2013-02-131-0/+1
| | | | | | | Fixed bug in tablegen conversion when source pseudo instruction has a different number of arguments than the destination instruction. llvm-svn: 175066
* Added 0x0D to 2-byte opcode extension table for prefetch* variantsKay Tiong Khoo2013-02-121-0/+1
| | | | | | | Fixed decode of existing 3dNow prefetchw instruction Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs llvm-svn: 174920
* Allow targets to add custom asm operand matching logic.Jim Grosbach2013-02-061-0/+9
| | | | | | | | | | For example, ARM has several instructions with a literal '#0' immediate in the syntax that's not represented as an actual operand. The asm matcher is expected a token operand, but the parser will have created an immediate operand. This is currently handled by dedicated per-instruction C++ munging of the ParsedAsmOperand list, but will be better handled by this hook. llvm-svn: 174487
* Fix commentsEli Bendersky2013-02-051-1/+1
| | | | llvm-svn: 174390
* This patch that sets the EmitAlias flag in td files Jack Carter2013-02-051-1/+4
| | | | | | | | | | | | | and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
* MachineModel: Inconsequential TableGen SubtargetEmitter fix.Andrew Trick2013-02-011-1/+15
| | | | | | | | Drive by fix. I noticed some missing logic that might bite future users. This shouldn't affect the final output on currently modeled targets. llvm-svn: 174142
* Clarify intent.Jakob Stoklund Olesen2013-01-311-0/+6
| | | | llvm-svn: 174068
* Add AArch64 as an experimental target.Tim Northover2013-01-311-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. llvm-svn: 174054
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