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* [X86] Part 2 to fix x86-64 fp128 calling convention.Chih-Hung Hsieh2015-12-141-0/+5
| | | | | | | | | | | | | | | | | | | | | | Part 1 was submitted in http://reviews.llvm.org/D15134. Changes in this part: * X86RegisterInfo.td, X86RecognizableInstr.cpp: Add FR128 register class. * X86CallingConv.td: Pass f128 values in XMM registers or on stack. * X86InstrCompiler.td, X86InstrInfo.td, X86InstrSSE.td: Add instruction selection patterns for f128. * X86ISelLowering.cpp: When target has MMX registers, configure MVT::f128 in FR128RegClass, with TypeSoftenFloat action, and custom actions for some opcodes. Add missed cases of MVT::f128 in places that handle f32, f64, or vector types. Add TODO comment to support f128 type in inline assembly code. * SelectionDAGBuilder.cpp: Fix infinite loop when f128 type can have VT == TLI.getTypeToTransformTo(Ctx, VT). * Add unit tests for x86-64 fp128 type. Differential Revision: http://reviews.llvm.org/D11438 llvm-svn: 255558
* [TableGen] Correct Namespace lookup with AltNames in AsmWriterEmitterHal Finkel2015-12-111-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | AsmWriterEmitter will generate a getRegisterName function with an alternate register name index as its second argument if the target makes use of them. The enum of these values is generated in RegisterInfoEmitter. The getRegisterName generator would assume the namespace could always be found by reading index 1 of the list of AltNameIndices, but this will fail if this list is sorted such that the NoRegAltName is at index 1. Because this list is sorted by record name (in CodeGenTarget::ReadRegAltNameIndices), you only run in to problems if your MyTargetRegisterInfo.td defines a single RegAltNameIndex that sorts lexically before NoRegAltName. For example, if a target has something like def AnAltNameIndex : RegAltNameIndex and defines RegAltNameIndices for some registers then, prior to this change, AsmWriterEmitter would generate references to ::AnAltNameIndex and ::NoRegAltName Patch by Alex Bradbury! llvm-svn: 255344
* Use make_range to reduce mentions of iterator type. NFCCraig Topper2015-12-062-7/+5
| | | | llvm-svn: 254872
* Replace uint16_t with the MCPhysReg typedef in many places. A lot of ↵Craig Topper2015-12-051-1/+1
| | | | | | physical register arrays already use this typedef. llvm-svn: 254843
* [TableGen] Remove an assumption about the order of encodings in the ↵Craig Topper2015-12-031-2/+13
| | | | | | MVT::SimpleValueType enum. Instead of assuming the types are sorted by size, scan the typeset arrays to find the smallest/largest type. NFC llvm-svn: 254589
* [AArch64] Add ARMv8.2-A Statistical Profiling ExtensionOliver Stannard2015-12-011-5/+7
| | | | | | | | | | | | The Statistical Profiling Extension is an optional extension to ARMv8.2-A. Since it is an optional extension, I have added the FeatureSPE subtarget feature to control it. The assembler-visible parts of this extension are the new "psb csync" instruction, which is equivalent to "hint #17", and a number of system registers. Differential Revision: http://reviews.llvm.org/D15021 llvm-svn: 254401
* [TableGen] Use SmallString instead of std::string to build up a string to ↵Craig Topper2015-11-281-2/+3
| | | | | | avoid heap allocations. NFC llvm-svn: 254221
* [TableGen] Sort pattern predicates before concatenating into a string so ↵Craig Topper2015-11-271-4/+11
| | | | | | that different orders of the same set will produce the same string. This can reduce the number of unique predicates in the isel tables. NFC llvm-svn: 254192
* [SelectionDAG] Add a SDTCisSameSizeAs type constraint that can be used to ↵Craig Topper2015-11-262-1/+73
| | | | | | ensure vector widths match even if the element size and count don't. llvm-svn: 254138
* [TableGen] Flip reversed comments.Craig Topper2015-11-261-2/+2
| | | | llvm-svn: 254136
* Add vector types for intrinsicsKrzysztof Parzyszek2015-11-241-1/+5
| | | | | Author: Ron Lieberman <ronl@codeaurora.org> llvm-svn: 253992
* Add names for the new vector types in CodeGenTarget.cppKrzysztof Parzyszek2015-11-241-0/+9
| | | | llvm-svn: 253989
* [TableGen] Use std::remove_if instead of manually coded loops that call ↵Craig Topper2015-11-241-74/+74
| | | | | | erase multiple times. NFC llvm-svn: 253964
* [TableGen] Use the other version of EnforceVectorEltTypeIs inside the ↵Craig Topper2015-11-241-15/+1
| | | | | | TypeSet version of EnforceVectorEltTypeIs to reduce duplicated code. NFC llvm-svn: 253963
* [TableGen] Fix formatting and use logical OR. NFCCraig Topper2015-11-241-2/+1
| | | | llvm-svn: 253962
* [TableGen] Use std::set_intersection to merge TypeSets. NFCCraig Topper2015-11-241-9/+8
| | | | llvm-svn: 253961
* [TableGen] Use SmallVector::assign instead of a resize and replace element.Craig Topper2015-11-241-2/+1
| | | | llvm-svn: 253960
* Revert change that accidentally snuck into r253955.Craig Topper2015-11-241-2/+1
| | | | llvm-svn: 253956
* [TableGen] Use array_pod_sort. NFCCraig Topper2015-11-241-2/+3
| | | | llvm-svn: 253955
* [TableGen] Use std::remove_if instead of manually coded loops that called ↵Craig Topper2015-11-231-15/+13
| | | | | | erase inside them. NFC llvm-svn: 253857
* [TableGen] Use empty() instead of checking if size of vector is greater than ↵Craig Topper2015-11-231-1/+2
| | | | | | or equal to 1. llvm-svn: 253856
* Revert a portion of r253836 that seems to have broke a couple bots.Craig Topper2015-11-221-11/+14
| | | | llvm-svn: 253838
* [TableGen] Use range-based for loops. NFCCraig Topper2015-11-221-127/+112
| | | | llvm-svn: 253836
* [TableGen] Use std::fill instead of a manually coded loop. NFCCraig Topper2015-11-221-2/+2
| | | | llvm-svn: 253835
* Further simplify from r253832 with some unique_ptr and coalescing conditionsDavid Blaikie2015-11-221-17/+12
| | | | llvm-svn: 253834
* Further simplify from r253832, removing unnecessary intermediate lambdasDavid Blaikie2015-11-221-16/+4
| | | | llvm-svn: 253833
* [TableGen] Use std::any_of and std::find instead of manual loops. NFCCraig Topper2015-11-221-32/+23
| | | | llvm-svn: 253832
* Avoid dependency between TableGen and CodeGenKrzysztof Parzyszek2015-11-221-1/+46
| | | | | | | | Duplicate a few common definitions between DFAPacketizer.cpp and DFAPacketizerEmitter.cpp to avoid including files from CodeGen in TableGen. llvm-svn: 253820
* Now fix errors in NDEBUG build.Krzysztof Parzyszek2015-11-211-33/+49
| | | | | | Hope this won't break any hardware next. llvm-svn: 253799
* Fix warnings in NDEBUG buildKrzysztof Parzyszek2015-11-211-8/+5
| | | | llvm-svn: 253798
* Hexagon V60/HVX DFA scheduler supportKrzysztof Parzyszek2015-11-211-107/+539
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extended DFA tablegen to: - added "-debug-only dfa-emitter" support to llvm-tblgen - defined CVI_PIPE* resources for the V60 vector coprocessor - allow specification of multiple required resources - supports ANDs of ORs - e.g. [SLOT2, SLOT3], [CVI_MPY0, CVI_MPY1] means: (SLOT2 OR SLOT3) AND (CVI_MPY0 OR CVI_MPY1) - added support for combo resources - allows specifying ORs of ANDs - e.g. [CVI_XLSHF, CVI_MPY01] means: (CVI_XLANE AND CVI_SHIFT) OR (CVI_MPY0 AND CVI_MPY1) - increased DFA input size from 32-bit to 64-bit - allows for a maximum of 4 AND'ed terms of 16 resources - supported expressions now include: expression => term [AND term] [AND term] [AND term] term => resource [OR resource]* resource => one_resource | combo_resource combo_resource => (one_resource [AND one_resource]*) Author: Dan Palermo <dpalermo@codeaurora.org> kparzysz: Verified AMDGPU codegen to be unchanged on all llc tests, except those dealing with instruction encodings. Reapply the previous patch, this time without circular dependencies. llvm-svn: 253793
* Revert r253790: it breaks all builds for some reason.Krzysztof Parzyszek2015-11-211-539/+107
| | | | llvm-svn: 253791
* Hexagon V60/HVX DFA scheduler supportKrzysztof Parzyszek2015-11-211-107/+539
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extended DFA tablegen to: - added "-debug-only dfa-emitter" support to llvm-tblgen - defined CVI_PIPE* resources for the V60 vector coprocessor - allow specification of multiple required resources - supports ANDs of ORs - e.g. [SLOT2, SLOT3], [CVI_MPY0, CVI_MPY1] means: (SLOT2 OR SLOT3) AND (CVI_MPY0 OR CVI_MPY1) - added support for combo resources - allows specifying ORs of ANDs - e.g. [CVI_XLSHF, CVI_MPY01] means: (CVI_XLANE AND CVI_SHIFT) OR (CVI_MPY0 AND CVI_MPY1) - increased DFA input size from 32-bit to 64-bit - allows for a maximum of 4 AND'ed terms of 16 resources - supported expressions now include: expression => term [AND term] [AND term] [AND term] term => resource [OR resource]* resource => one_resource | combo_resource combo_resource => (one_resource [AND one_resource]*) Author: Dan Palermo <dpalermo@codeaurora.org> kparzysz: Verified AMDGPU codegen to be unchanged on all llc tests, except those dealing with instruction encodings. llvm-svn: 253790
* Default SetVector to use a DenseSet.Rafael Espindola2015-11-182-5/+5
| | | | | | | | | | | | | | | We use to have an odd difference among MapVector and SetVector. The map used a DenseMop, but the set used a SmallSet, which in turn uses a std::set. I have changed SetVector to use a DenseSet. If you were depending on the old behaviour you can pass an explicit set type or use SmallSetVector. The common cases for needing to do it are: * Optimizing for small sets. * Sets for types not supported by DenseSet. llvm-svn: 253439
* Assume lane masks are always preciseMatthias Braun2015-11-171-13/+6
| | | | | | | | | | | | | | | Allowing imprecise lane masks in case of more than 32 sub register lanes lead to some tricky corner cases, and I need another bugfix for another one. Instead I rather declare lane masks as precise and let tablegen abort if we do not have enough bits. This does not affect any in-tree target, even AMDGPU only needs 16 lanes at the moment. If the 32 lanes turn out to be a problem in the future, then we can easily change the LaneBitmask typedef to uint64_t. Differential Revision: http://reviews.llvm.org/D14557 llvm-svn: 253279
* [MCTargetAsmParser] Move the member varialbes that referenceAkira Hatanaka2015-11-141-1/+1
| | | | | | | | | | MCSubtargetInfo in the subclasses into MCTargetAsmParser and define a member function getSTI. This is done in preparation for making changes to shrink the size of MCRelaxableFragment. (see http://reviews.llvm.org/D14346). llvm-svn: 253124
* tablegen: Add a simple heuristic to get better names for pressure setsMatthias Braun2015-11-131-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D14597 llvm-svn: 253095
* Revert r252990.Akira Hatanaka2015-11-131-95/+0
| | | | | | Some of the buildbots are still failing. llvm-svn: 252999
* Provide a way to specify inliner's attribute compatibility and merging.Akira Hatanaka2015-11-131-0/+95
| | | | | | | | | | | | | | | | | | This reapplies r252949. I've changed the type of FuncName to be std::string instead of StringRef in emitFnAttrCompatCheck. Original commit message for r252949: Provide a way to specify inliner's attribute compatibility and merging rules using table-gen. NFC. This commit adds new classes CompatRule and MergeRule to Attributes.td, which are used to generate code to check attribute compatibility and merge attributes of the caller and callee. rdar://problem/19836465 llvm-svn: 252990
* Revert r252949.Akira Hatanaka2015-11-121-95/+0
| | | | | | It broke some of the bots including clang-x64-ninja-win7. llvm-svn: 252951
* Provide a way to specify inliner's attribute compatibility and mergingAkira Hatanaka2015-11-121-0/+95
| | | | | | | | | | | | rules using table-gen. NFC. This commit adds new classes CompatRule and MergeRule to Attributes.td, which are used to generate code to check attribute compatibility and merge attributes of the caller and callee. rdar://problem/19836465 llvm-svn: 252949
* Move the enum attributes defined in Attributes.h to a table-gen file.Akira Hatanaka2015-11-114-1/+68
| | | | | | | | | | | | | | This is a step towards consolidating some of the information regarding attributes in a single place. This patch moves the enum attributes in Attributes.h to the table-gen file. Additionally, it adds definitions of target independent string attributes that will be used in follow-up commits by the inliner to check attribute compatibility. rdar://problem/19836465 llvm-svn: 252796
* TableGen: Emit LaneMask for register classes without subregisters as ~0uMatthias Braun2015-11-101-0/+6
| | | | | | | This makes it slightly easier to handle classes with and without subregister uniformly. llvm-svn: 252671
* [AsmParser] Generalize matching for grammars without mnemonic-lead statementsColin LeMahieu2015-11-091-35/+31
| | | | | | Differential Revision: http://reviews.llvm.org/D14257 llvm-svn: 252440
* [AsmParser] Backends can parameterize ASM tokenization.Colin LeMahieu2015-11-091-47/+68
| | | | llvm-svn: 252439
* Fix some Clang-tidy modernize warnings, other minor fixes.Eugene Zelenko2015-11-041-10/+10
| | | | | | | | Fixed warnings are: modernize-use-override, modernize-use-nullptr and modernize-redundant-void-arg. Differential revision: http://reviews.llvm.org/D14312 llvm-svn: 252087
* [TblGen] ArrayRefize CodeGenSchedule. No functionality change intended.Benjamin Kramer2015-10-242-69/+61
| | | | llvm-svn: 251187
* [IntrinsicEmitter] Remove GET_INTRINSIC_MODREF_BEHAVIOR tableIgor Laevsky2015-10-221-41/+0
| | | | | | | | | There is no need to generate separate table for intrinsics mod ref behaviour. It can now be determined purely from function attributes. Differential Revision: http://reviews.llvm.org/D13917 llvm-svn: 251040
* [TableGen] Add a space between type and '*' in front of a variable name in ↵Craig Topper2015-10-111-1/+1
| | | | | | output file. While there replace type with 'auto' since there's a cast on the right side of the assignment. NFC llvm-svn: 249980
* Fix Clang-tidy modernize-use-nullptr warnings in source directories and ↵Hans Wennborg2015-10-061-8/+9
| | | | | | | | | | generated files; other minor cleanups. Patch by Eugene Zelenko! Differential Revision: http://reviews.llvm.org/D13321 llvm-svn: 249482
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