summaryrefslogtreecommitdiffstats
path: root/llvm/utils/TableGen
Commit message (Collapse)AuthorAgeFilesLines
* [Bash-autocompletion] Add support for static analyzer flagsYuka Takahashi2017-08-231-0/+26
| | | | | | | | | | | | | | | | | | | | | | Summary: This is a patch for clang autocomplete feature. It will collect values which -analyzer-checker takes, which is defined in clang/StaticAnalyzer/Checkers/Checkers.inc, dynamically. First, from ValuesCode class in Options.td, TableGen will generate C++ code in Options.inc. Options.inc will be included in DriverOptions.cpp, and calls OptTable's addValues function. addValues function will add second argument to Option's Values class. Values contains string like "foo,bar,.." which is handed to Values class in OptTable. Reviewers: v.g.vassilev, teemperor, ruiu Subscribers: hiraditya, cfe-commits Differential Revision: https://reviews.llvm.org/D36782 llvm-svn: 311552
* [globalisel][tablegen] Add support for ImmLeaf without SDNodeXFormDaniel Sanders2017-08-231-13/+124
| | | | | | | | | | | | | | | | | | | Summary: This patch adds support for predicates on imm nodes but only for ImmLeaf and not for PatLeaf or PatFrag and only where the value does not need to be transformed before being rendered into the instruction. The limitation on PatLeaf/PatFrag/SDNodeXForm is due to differences in the necessary target-supplied C++ for GlobalISel. Depends on D36085 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36086 llvm-svn: 311546
* [globalisel][tablegen] Add tests for FeatureBitsets and ComplexPattern ↵Daniel Sanders2017-08-231-3/+6
| | | | | | predicates. llvm-svn: 311542
* [AVX512] Add 128->256 vbroadcastf64x2/vbroadcasti64x2 instructions to the ↵Craig Topper2017-08-211-0/+3
| | | | | | EVEX->VEX table. llvm-svn: 311307
* [globalisel][tablegen] Generate TypeObject table. NFCDaniel Sanders2017-08-171-33/+29
| | | | | | | | | | | | | | | | | | Summary: Generate the type table from the types used by a target rather than hard-coding the union of types used by all targets. Depends on D36084 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36085 llvm-svn: 311084
* Re-commit: [globalisel][tablegen] Support zero-instruction emission.Daniel Sanders2017-08-171-40/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on Windows machines due to a flaw in the sort predicate which allowed both A < B < C and B == C to be satisfied simultaneously. The cause of this was some sloppiness in the priority order of G_CONSTANT instructions compared to other instructions. These had equal priority because it makes no difference, however there were operands had higher priority than G_CONSTANT but lower priority than any other instruction. As a result, a priority order between G_CONSTANT and other instructions must be enforced to ensure the predicate defines a strict weak order. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 311076
* Revert r310919 - [globalisel][tablegen] Support zero-instruction emission.Daniel Sanders2017-08-151-100/+60
| | | | | | | | | | As expected, this failed on the windows bots but the instrumentation showed something interesting. The ADD8ri and INC8r rules are never directly compared on the windows machines. That implies that the issue lies in transitivity of the Compare predicate. I believe I've already verified that but maybe I missed something. llvm-svn: 310922
* Re-commit with some instrumentation: [globalisel][tablegen] Support ↵Daniel Sanders2017-08-151-60/+100
| | | | | | | | | | | | | | | | | | | | | | | | | zero-instruction emission. Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on the windows bots and this one is likely to fail on those same bots. However, the added instrumentation should reveal a particular isHigherPriorityThan() evaluation which I'm expecting to expose that these machines are weighing priority of two rules differently from the non-windows machines. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 310919
* Revert r310716 (and r310735): [globalisel][tablegen] Support ↵Daniel Sanders2017-08-111-65/+50
| | | | | | | | | | | zero-instruction emission. Two of the Windows bots are failing test\CodeGen\X86\GlobalISel\select-inc.mir which should not have been affected by the change. Reverting while I investigate. Also reverted r310735 because it builds on r310716. llvm-svn: 310745
* [globalisel][tablegen] Generate TypeObject table. NFCDaniel Sanders2017-08-111-33/+29
| | | | | | | | | | | | | | | | | | Summary: Generate the type table from the types used by a target rather than hard-coding the union of types used by all targets. Depends on D36084 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36085 llvm-svn: 310735
* [globalisel][tablegen] Support zero-instruction emission.Daniel Sanders2017-08-111-25/+44
| | | | | | | | | | | | | | | | | | | Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. Depends on D35833 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 310716
* [globalisel][tablegen] Remove unnecessary ; to satisfy ubuntu-gcc7.1-werror.Daniel Sanders2017-08-081-1/+1
| | | | llvm-svn: 310357
* [globalisel][tablegen] Add support for importing 'imm' operands.Daniel Sanders2017-08-081-15/+122
| | | | | | | | | | | | | | | | | | | Summary: This patch enables the import of rules containing 'imm' operands that do not constrain the acceptable values using predicates. Support for ImmLeaf will arrive in a later patch. Depends on D35681 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35833 llvm-svn: 310343
* [TableGen] AsmMatcher: fix OpIdx computation when HasOptionalOperands is trueNirav Dave2017-08-071-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Relanding after fixing UB issue with DefaultOffsets. Consider the following instruction: "inst.eq $dst, $src" where ".eq" is an optional flag operand. The $src and $dst operands are registers. If we parse the instruction "inst r0, r1", the flag is not present and it will be marked in the "OptionalOperandsMask" variable. After the matching is complete we call the "convertToMCInst" method. The current implementation works only if the optional operands are at the end of the array. The "Operands" array looks like [token:"inst", reg:r0, reg:r1]. The first operand that must be added to the MCInst is the destination, the r0 register. The "OpIdx" (in the Operands array) for this register is 2. However, since the flag is not present in the Operands, the actual index for r0 should be 1. The flag is not present since we rely on the default value. This patch removes the "NumDefaults" variable and replaces it with an array (DefaultsOffset). This array contains an index for each operand (excluding the mnemonic). At each index, the array contains the number of optional operands that should be subtracted. For the previous example, this array looks like this: [0, 1, 1]. When we need to access the r0 register, we compute its index as 2 - DefaultsOffset[1] = 1. Patch by Alexandru Guduleasa! Reviewers: SamWot, nhaustov, niravd Reviewed By: niravd Subscribers: vitalybuka, llvm-commits Differential Revision: https://reviews.llvm.org/D35998 llvm-svn: 310254
* Revert "[TableGen] AsmMatcher: fix OpIdx computation when ↵Vitaly Buka2017-08-041-19/+3
| | | | | | | | | | HasOptionalOperands is true" Breaks check-llvm under ubsan. This reverts commit r309949. llvm-svn: 310008
* [TableGen] AsmMatcher: fix OpIdx computation when HasOptionalOperands is trueNirav Dave2017-08-031-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consider the following instruction: "inst.eq $dst, $src" where ".eq" is an optional flag operand. The $src and $dst operands are registers. If we parse the instruction "inst r0, r1", the flag is not present and it will be marked in the "OptionalOperandsMask" variable. After the matching is complete we call the "convertToMCInst" method. The current implementation works only if the optional operands are at the end of the array. The "Operands" array looks like [token:"inst", reg:r0, reg:r1]. The first operand that must be added to the MCInst is the destination, the r0 register. The "OpIdx" (in the Operands array) for this register is 2. However, since the flag is not present in the Operands, the actual index for r0 should be 1. The flag is not present since we rely on the default value. This patch removes the "NumDefaults" variable and replaces it with an array (DefaultsOffset). This array contains an index for each operand (excluding the mnemonic). At each index, the array contains the number of optional operands that should be subtracted. For the previous example, this array looks like this: [0, 1, 1]. When we need to access the r0 register, we compute its index as 2 - DefaultsOffset[1] = 1. Patch by Alexandru Guduleasa! Reviewers: SamWot, nhaustov, niravd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35998 llvm-svn: 309949
* [GlobalISel] Only merge memory ops for mayLoad or mayStore instrs.Florian Hahn2017-08-031-18/+21
| | | | | | | | | | | | | | | | Summary: We only need to merge memory operands for instructions that access memory. This slightly reduces the number of actions executed. Reviewers: MatzeB, rovka, dsanders Reviewed By: dsanders Subscribers: aemerson, igorb, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D36151 llvm-svn: 309944
* [globalisel][tablegen] Do not merge memoperands from instructions that ↵Daniel Sanders2017-08-021-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | weren't in the match. Summary: Fix a bug discovered in an out-of-tree target where memoperands from pseudo-instructions that weren't part of the match were being merged into the result instructions as part of GIR_MergeMemOperands. This bug was caused by a change to the handling of State.MIs between rules when the state machine tables were fused into a single table. Previously, each rule would reset State.MIs using State.MIs.resize(1) but this is no longer done, as a result stale data is occasionally left in some elements of State.MIs. Most opcodes aren't affected by this but GIR_MergeMemOperands merges all memoperands from the intructions recorded in State.MIs into the result instruction. Suppose for example, we processed but rejected the following pattern: (signextend (load x)) at this point, State.MIs contains the signextend and the load. Now suppose we process and accept this pattern: (add x, y) at this point, State.MIs contains the add as well as the (now irrelevant) load. When GIR_MergeMemOperands is processed, the memoperands from that irrelevant load will be merged into the result instruction even though it was not part of the match. Bringing back the State.MIs.resize(1) would fix the problem but it would limit our ability to optimize the table in the future. Instead, this patch fixes the problem by explicitly stating which instructions should be merged into the result. There's no direct test case in this commit because a test case would be very brittle. However, at the time of writing this should fix the failures in http://green.lab.llvm.org/green/job/Compiler_Verifiers_GlobalISEL/ as well as a failure in test/CodeGen/ARM/GlobalISel/arm-isel.ll when expensive checks are enabled. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: fhahn, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36094 llvm-svn: 309804
* NFC: spell correction.Lama Saba2017-07-301-1/+1
| | | | | | | | On behalf of jbhateja Differential Revision: https://reviews.llvm.org/D35885 llvm-svn: 309521
* [globalisel][tablegen] Ensure MatchTable's are compile-time constants with ↵Daniel Sanders2017-07-271-1/+1
| | | | | | | | | constexpr. NFC. This should prevent any re-occurence of the problem where the table was initialized at run-time. llvm-svn: 309267
* Re-commit: r309094 [globalisel][tablegen] Fuse the generated tables together.Daniel Sanders2017-07-271-28/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Now that we have control flow in place, fuse the per-rule tables into a single table. This is a compile-time saving at this point. However, this will also enable the optimization of a table so that similar instructions can be tested together, reducing the time spent on the matching the code. This is NFC in terms of externally visible behaviour but some internals have changed slightly. State.MIs is no longer reset between each rule that is attempted because it's not necessary to do so. As a consequence of this the restriction on the order that instructions are added to State.MIs has been relaxed to only affect recorded instructions that require new elements to be added to the vector. GIM_RecordInsn can now write to any element from 1 to State.MIs.size() instead of just State.MIs.size(). The compile-time regressions from the last commit were caused by the ARM target including a non-const variable (zero_reg) in the table and therefore generating an initializer for it. That variable is now const. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35681 llvm-svn: 309264
* Revert r309094: [globalisel][tablegen] Fuse the generated tables together.Daniel Sanders2017-07-261-26/+28
| | | | | | | | The ARM bots have started failing and while this patch should be an improvement for these bots, it's also the only suspect in the blamelist. Reverting while Diana and I investigate the problem. llvm-svn: 309111
* [globalisel][tablegen] Fuse the generated tables together.Daniel Sanders2017-07-261-28/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Now that we have control flow in place, fuse the per-rule tables into a single table. This is a compile-time saving at this point. However, this will also enable the optimization of a table so that similar instructions can be tested together, reducing the time spent on the matching the code. This is NFC in terms of externally visible behaviour but some internals have changed slightly. State.MIs is no longer reset between each rule that is attempted because it's not necessary to do so. As a consequence of this the restriction on the order that instructions are added to State.MIs has been relaxed to only affect recorded instructions that require new elements to be added to the vector. GIM_RecordInsn can now write to any element from 1 to State.MIs.size() instead of just State.MIs.size(). Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35681 llvm-svn: 309094
* Implement LaneBitmask::getNumLanes and LaneBitmask::getHighestLaneKrzysztof Parzyszek2017-07-201-6/+2
| | | | | | | This should eliminate most uses of countPopulation and Log2_32 on the lane mask values. llvm-svn: 308658
* [globalisel][tablegen] Add control-flow to the MatchTable.Daniel Sanders2017-07-201-119/+411
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This will allow us to merge the various sub-tables into a single table. This is a compile-time saving at this point. However, this will also enable the optimization of a table so that similar instructions can be tested together, reducing the time spent on the matching the code. The bulk of this patch is a mechanical conversion to the new MatchTable object which is responsible for tracking label definitions and filling in the index of the jump targets. It is also responsible for nicely formatting the table. This was necessary to support the new GIM_Try opcode which takes the index to jump to if the match should fail. This value is unknown during table construction and is filled in during emission. To support nesting try-blocks (although we currently don't emit tables with nested try-blocks), GIM_Reject has been re-introduced to explicitly exit a try-block or fail the overall match if there are no active try-blocks. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35117 llvm-svn: 308596
* [TableGen][MC] Fix a few places where we didn't hide the underlying type of ↵Craig Topper2017-07-141-6/+6
| | | | | | | | | | LaneBitmask very well. One place compared with 32, which I've replaced with LaneBitmask::BitWidth. The other places are shifts of a constant 1 by a lane number. But if LaneBitmask were to be a larger type than 32-bits like 64-bits, the 1 would need to be 1ULL to do a 64-bit shift. To hide this I've added a LanebitMask::getLane that hides the shift and make sures the 1 is casted to correct type first. llvm-svn: 308042
* [globalisel][tablegen] Fix an multi-insn match bug where ComplexPattern is ↵Daniel Sanders2017-07-111-7/+11
| | | | | | | | | | | | | | | | | | | | | | used on multiple insns. In each rule, each use of ComplexPattern is assigned an element in the Renderers array. The matcher then collects renderer functions in this array and they are used to render instructions. This works well for a single instruction but a bug in the allocation mechanism causes the elements to be assigned on a per-instruction basis rather than a per-rule basis. So in the case of: (set GPR32:$dst, (Op complex:$src1, complex:$src2)) tablegen currently assigns elements 0 and 1 to $src1 and $src2 respectively, but for: (set GPR32:$dst, (Op complex:$src1, (Op complex:$src2))) it currently assigned both $src1 and $src2 the same element (0). This results in one complex operand being rendered twice and the other being forgotten. This patch corrects the allocation such that $src1 and $src2 are still allocated different elements in this case. llvm-svn: 307646
* [globalisel][tablegen] Correct matching of intrinsic ID's.Daniel Sanders2017-07-111-6/+23
| | | | | | | | | | | | TreePatternNode considers them to be plain integers but MachineInstr considers them to be a distinct kind of operand. The tweak to AArch64InstrInfo.td to produce a simple test case is a NFC for everything except GlobalISelEmitter (confirmed by diffing the tablegenerated files). GlobalISelEmitter is currently unable to infer the type of operands in the Dst pattern from the operands in the Src pattern. llvm-svn: 307634
* [TableGen] Cleanup capturing of instruction namespace for the fast isel ↵Craig Topper2017-07-071-11/+7
| | | | | | emitter to remove a std::string and duplicated code. NFC llvm-svn: 307363
* [TableGen] Use StringRef instead of std::string for CodeGenInstruction ↵Craig Topper2017-07-078-16/+16
| | | | | | namespace. NFC llvm-svn: 307362
* [TableGen] Fix some mismatches in the use of Namespace fields versus Target ↵Craig Topper2017-07-072-3/+3
| | | | | | | | | | | | name in some of our emitters. Some of our emitters were using the name of the Target to reference things that were created by others emitters using Namespace. Apparently all targets have the same Target name as their instruction and register Namespace field? Someone on IRC had a target that didn't do this and was getting build errors. This patch is a necessary, but maybe not sufficient fix. llvm-svn: 307358
* [globalisel][tablegen] Rename and re-comment render functions to match the ↵Daniel Sanders2017-07-061-7/+7
| | | | | | | | | | new MatchTables. NFC. The conversion to MatchTable left the function names and comments referring to C++ statements and expressions. Updated the names and comments to account for the fact that they're no longer unconstrained statements/expressions. llvm-svn: 307248
* [globalisel][tablegen] Rename and re-comment to match the new MatchTables. NFC.Daniel Sanders2017-07-061-46/+47
| | | | | | | | The conversion to MatchTable left the function names and comments referring to C++ statements and expressions. Updated the names and comments to account for the fact that they're no longer unconstrained statements/expressions. llvm-svn: 307246
* [globalisel][tablegen] Import rules containing intrinsic_wo_chain.Daniel Sanders2017-07-061-4/+27
| | | | | | | | | | | | | | | | | Summary: As of this patch, 1018 out of 3938 rules are currently imported. Depends on D32275 Reviewers: qcolombet, kristof.beyls, rovka, t.p.northover, ab, aditya_nandakumar Reviewed By: qcolombet Subscribers: dberris, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32278 llvm-svn: 307240
* [tablegen] Avoid creating temporary stringsAlexander Shaposhnikov2017-07-054-15/+10
| | | | | | | | | | | | | If a method / function returns a StringRef but the variable is of type const std::string& a temporary string is created (StringRef has a cast operator to std::string), which is a suboptimal behavior. Differential revision: https://reviews.llvm.org/D34994 Test plan: make check-all llvm-svn: 307195
* [globalisel][tablegen] Finish fixing compile-time regressions by merging the ↵Daniel Sanders2017-07-051-36/+26
| | | | | | | | | | | | | | | | | | | | | | | matcher and emitter state machines. Summary: Also, made a few minor tweaks to shave off a little more cumulative memory consumption: * All rules share a single NewMIs instead of constructing their own. Only one will end up using it. * Use MIs.resize(1) instead of MIs.clear();MIs.push_back(I) and prevent GIM_RecordInsn from changing MIs[0]. Depends on D33764 Reviewers: rovka, vitalybuka, ab, t.p.northover, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33766 llvm-svn: 307159
* [AsmParser] Mnemonic Spell CorrectorSjoerd Meijer2017-07-051-0/+43
| | | | | | | | | | | | | | | | | | This implements suggesting other mnemonics when an invalid one is specified, for example: $ echo "adXd r1,r2,#3" | llvm-mc -triple arm <stdin>:1:1: error: invalid instruction, did you mean: add, qadd? adXd r1,r2,#3 ^ The implementation is target agnostic, but as a first step I have added it only to the ARM backend; so the ARM backend is a good example if someone wants to enable this too for another target. Differential Revision: https://reviews.llvm.org/D33128 llvm-svn: 307148
* [globalisel][tablegen] Fix the misuse of STATISTICS() on release builds ↵Daniel Sanders2017-07-051-4/+4
| | | | | | | | | | | | (like r307088) after r307133. r307133 brought back a couple instances of the same mistake that was already fixed by r307088. Fixed it again. Using NumPatternEmitted as a unique id for the tables is not valid on release builds since the counters don't count in that case. llvm-svn: 307146
* [globalisel][tablegen] Added instruction emission to the state-machine-based ↵Daniel Sanders2017-07-051-105/+105
| | | | | | | | | | | | | | | | | | | | | | | matcher. Summary: This further improves the compile-time regressions that will be caused by a re-commit of r303259. Also added included preliminary work in preparation for the multi-insn emitter since I needed to change the relevant part of the API for this patch anyway. Depends on D33758 Reviewers: rovka, vitalybuka, ab, t.p.northover, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33764 llvm-svn: 307133
* [globalisel][tablegen] Fix release builds after r307079Daniel Sanders2017-07-041-2/+7
| | | | | | | | | Using NumPatternEmitted as a unique id for the tables is not valid on release builds since the counters don't count in that case. Also fix an unused variable warning. llvm-svn: 307088
* [globalisel][tablegen] Partially fix compile-time regressions by converting ↵Daniel Sanders2017-07-041-156/+299
| | | | | | | | | | | | | | | | | | | | | | matcher to state-machine(s) Summary: Replace the matcher if-statements for each rule with a state-machine. This significantly reduces compile time, memory allocations, and cumulative memory allocation when compiling AArch64InstructionSelector.cpp.o after r303259 is recommitted. The following patches will expand on this further to fully fix the regressions. Reviewers: rovka, ab, t.p.northover, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: vitalybuka, aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33758 llvm-svn: 307079
* fix trivial typos in comments; NFCHiroshi Inoue2017-07-045-5/+5
| | | | llvm-svn: 307075
* [tablegen] Avoid creating a temporary vector in getInstructionCaseAlexander Shaposhnikov2017-07-041-8/+6
| | | | | | | | | | | | | Record::getValues returns ArrayRef which has a cast operator to std::vector, as a result a temporary vector is created if the type of the variable is const std::vector& that is suboptimal in this case. Differential revision: https://reviews.llvm.org/D34969 Test plan: make check-all llvm-svn: 307063
* Remove `inline` keyword from inline `classof` methodsSam Clegg2017-06-291-35/+35
| | | | | | | | | | | | | | | | | | | | | | The style guide states that the explicit `inline` should not be used with inline methods. classof is very common inline method with a fair amount on inconsistency: $ git grep classof ./include | grep inline | wc -l 230 $ git grep classof ./include | grep -v inline | wc -l 257 I chose to target this method rather the larger change since this method is easily cargo-culted (I did it at least once). I considered doing the larger change and removing all occurrences but that would be a much larger change. Differential Revision: https://reviews.llvm.org/D33906 llvm-svn: 306731
* Break up long lines, NFCKrzysztof Parzyszek2017-06-281-2/+4
| | | | llvm-svn: 306585
* [globalisel][tablegen] Post-commit review nits for r306388. NFCDaniel Sanders2017-06-281-37/+31
| | | | | | One early exit and a missing assert string. llvm-svn: 306552
* [globalisel][tablegen] Multiple 80-col corrections.Daniel Sanders2017-06-281-20/+41
| | | | llvm-svn: 306544
* [TableGen] Improve Debug Output for --debug-only=subtarget-emitter NFCIJoel Jones2017-06-282-0/+8
| | | | | | | | | Add headers for each section of output, with white space and "+++" to improve readability. Differential Revision: https://reviews.llvm.org/D34713 llvm-svn: 306492
* Change sort function used in tblgen to be strict weak orderingDavid Green2017-06-271-1/+1
| | | | | | | The windows debug is failing as the sort function is not strict weak ordering, so switch a >= to a >. llvm-svn: 306422
* [globalisel][tablegen] Add support for EXTRACT_SUBREG.Daniel Sanders2017-06-273-10/+236
| | | | | | | | | | | | | | | | Summary: After this patch, we finally have test cases that require multiple instruction emission. Depends on D33590 Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls Subscribers: javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D33596 llvm-svn: 306388
OpenPOWER on IntegriCloud