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* Compress tables for getMatchingSuperRegClass().Jakob Stoklund Olesen2012-05-031-19/+67
| | | | | | | | Many register classes only have a few super-registers, so it is not necessary to keep individual bit masks for all possible sub-register indices. llvm-svn: 156083
* Don't override subreg functions in targets without subregisters.Jakob Stoklund Olesen2012-05-031-42/+39
| | | | | | | | Some targets have no sub-registers at all. Use the TargetRegisterInfo versions of composeSubRegIndices(), getSubClassWithSubReg(), and getMatchingSuperRegClass() for those targets. llvm-svn: 156075
* Move llvm-tblgen's StringMatcher into the TableGen library so it canDouglas Gregor2012-05-025-206/+2
| | | | | | be used by clang-tblgen. llvm-svn: 156000
* Add ifdef around getSubtargetFeatureName in tablegen output file so that ↵Craig Topper2012-04-251-3/+7
| | | | | | only targets that want the function get it. This prevents other targets from getting an unused function warning. llvm-svn: 155538
* ARM: improved assembler diagnostics for missing CPU features.Jim Grosbach2012-04-241-2/+26
| | | | | | | | | | | When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 llvm-svn: 155499
* Remove 'XXXRegisterClass' from tablegen output. Targets should use ↵Craig Topper2012-04-211-3/+0
| | | | | | '&XXXRegClass' instead. llvm-svn: 155270
* TableGen'd RegPressure: Added getPressureSetName.Andrew Trick2012-04-201-1/+13
| | | | llvm-svn: 155234
* TableGen support for auto-generating assembly two-operand aliases.Jim Grosbach2012-04-191-2/+97
| | | | | | | | | | | | | | Assembly matchers for instructions with a two-operand form. ARM is full of these, for example: add {Rd}, Rn, Rm // Rd is optional and is the same as Rn if omitted. The property TwoOperandAliasConstraint on the instruction definition controls when, and if, an alias will be formed. No explicit InstAlias definitions are required. rdar://11255754 llvm-svn: 155172
* Use a SmallVector instead of std::vector for ResOperands.Jim Grosbach2012-04-191-2/+2
| | | | | | | There's almost always a small number of instruction operands, so use a SmallVector and save on heap allocations. llvm-svn: 155143
* Update some internal naming conventions to modern style.Jim Grosbach2012-04-191-85/+85
| | | | llvm-svn: 155142
* Make fast isel use &XXXRegClass instead of XXXRegisterClass. Not a ↵Craig Topper2012-04-191-2/+2
| | | | | | functional change since XXXRegisterClass is just a constant alias of &XXXRegClass, but should probably go away. llvm-svn: 155104
* Fix typo.Jim Grosbach2012-04-181-1/+1
| | | | llvm-svn: 155075
* Revert "Replace some uses of std:map<std::string,...> with StringMap."Jim Grosbach2012-04-181-6/+6
| | | | | | | StringMap iterators are not deterministic, and that's more important here than speed or memory. llvm-svn: 155039
* tblgen: remove duplicated newlines.Benjamin Kramer2012-04-183-6/+6
| | | | llvm-svn: 155038
* Replace some uses of std:map<std::string,...> with StringMap.Jim Grosbach2012-04-181-6/+6
| | | | llvm-svn: 155037
* Use SmallVector for the requirements on an InstAlias.Jim Grosbach2012-04-181-1/+1
| | | | llvm-svn: 155034
* Tidy up. Formatting.Jim Grosbach2012-04-181-2/+3
| | | | llvm-svn: 155032
* Move a few more warnings to use PrintWarning().Jim Grosbach2012-04-182-7/+9
| | | | llvm-svn: 155027
* Tidy up. No need for a Twine here, as it's just constants.Jim Grosbach2012-04-181-4/+4
| | | | llvm-svn: 155026
* Formatting.Jim Grosbach2012-04-181-3/+2
| | | | llvm-svn: 155025
* Tidy up. Add a '.' at the end of the sentence.Jim Grosbach2012-04-181-1/+1
| | | | llvm-svn: 155024
* Clean up warning text. Remove extraneous prefix.Jim Grosbach2012-04-181-4/+4
| | | | llvm-svn: 155015
* TableGen use PrintWarning rather than fprintf(stderr,...) for warnings.Jim Grosbach2012-04-181-12/+13
| | | | | | That way we get source line number information from the diagnostics. llvm-svn: 155014
* Fixed decoding for the ARM cdp2 instruction. The restriction on the ↵Silviu Baranga2012-04-181-0/+1
| | | | | | coprocessor number was removed for this instruction. llvm-svn: 155000
* Sanity check error handling for TokenAlias.Jim Grosbach2012-04-171-0/+3
| | | | llvm-svn: 154951
* Tidy up. 80 columns.Jim Grosbach2012-04-171-7/+9
| | | | llvm-svn: 154881
* Fix target specific intrinsic handling to adjust intrinsic number before ↵Craig Topper2012-04-131-9/+15
| | | | | | doing attribute table lookup. Also fix attribute table lookup to handle 'invalid' intrinsic correctly. Fixes PR12542 llvm-svn: 154658
* Remove incorrect comment.Jim Grosbach2012-04-111-1/+1
| | | | llvm-svn: 154533
* Tidy up. Remove hard tab characters.Jim Grosbach2012-04-111-28/+28
| | | | llvm-svn: 154532
* Tidy up. Whitespace.Jim Grosbach2012-04-112-5/+5
| | | | llvm-svn: 154531
* TableGen's regpressure: emit per-registerclass weight limits.Andrew Trick2012-04-113-27/+38
| | | | llvm-svn: 154518
* TableGen'd regpressure: register unit set pruning.Andrew Trick2012-04-111-18/+14
| | | | | | | The pruning is more complete if it is not done incrementally. The code is also a tad less convluted. llvm-svn: 154510
* Tablegen'd regpressure: emit the weighted pressure limit.Andrew Trick2012-04-111-1/+7
| | | | llvm-svn: 154477
* Table-generated register pressure fixes.Andrew Trick2012-04-111-24/+47
| | | | | | | Handle mixing allocatable and unallocatable register gracefully. Simplify the pruning of register unit sets. llvm-svn: 154474
* TableGen/reginfo potential bug: typo from previous checkin.Andrew Trick2012-04-101-1/+1
| | | | llvm-svn: 154452
* Fix for register pressure tables.Andrew Trick2012-04-101-13/+15
| | | | | | Recent refactoring introduced a bug. Fix: added buildRegUnitSets. llvm-svn: 154382
* Use std::includes instead of my own implementation.Andrew Trick2012-04-101-9/+2
| | | | | | Jakob's review. llvm-svn: 154377
* Added register unit sets to the target description.Andrew Trick2012-04-104-0/+292
| | | | | | | | | | This is a new algorithm that finds sets of register units that can be used to model registers pressure. This handles arbitrary, overlapping register classes. Each register class is associated with a (small) list of pressure sets. These are the dimensions of pressure affected by the register class's liveness. llvm-svn: 154374
* Added register unit weights to the target description.Andrew Trick2012-04-102-19/+352
| | | | | | | | | | | | This is a new algorithm that associates registers with weighted register units to accuretely model their effect on register pressure. This handles registers with multiple overlapping subregisters. It is possible, but almost inconceivable that the algorithm fails to find an exact solution for a target description. If an exact solution cannot be found, an inexact, but reasonable solution will be chosen. llvm-svn: 154373
* Fix header commentAndrew Trick2012-04-101-2/+2
| | | | llvm-svn: 154372
* Convert assert(false) followed by a return to llvm_unreachableCraig Topper2012-04-041-2/+1
| | | | llvm-svn: 153997
* Tidy up spacing in some tablegen outputs.Craig Topper2012-04-032-11/+9
| | | | llvm-svn: 153937
* Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.Craig Topper2012-04-032-0/+3
| | | | llvm-svn: 153935
* Cleanup set_union usage. The same thing but a bit cleaner now.Andrew Trick2012-04-031-1/+1
| | | | llvm-svn: 153922
* Use std::set_union instead of nasty custom code.Andrew Trick2012-04-031-13/+3
| | | | | | | I just noticed Jakob's examples of the proper application of std::set... routines. llvm-svn: 153918
* Second part for the 153874 oneSilviu Baranga2012-04-021-3/+3
| | | | llvm-svn: 153875
* Emit the asm writer's mnemonic table with SequenceToOffsetTable.Benjamin Kramer2012-04-021-6/+21
| | | | | | This way we can get AVX v-prefixed instructions tail merged with the normal insns. llvm-svn: 153869
* Reorder fields in MatchEntry and OperandMatchEntry to reduce padding. A bit ↵Craig Topper2012-04-021-24/+25
| | | | | | tricky due to the target specific sizes for some of the fields so the ordering is only optimal for the targets in the tree. llvm-svn: 153865
* Remove getInstructionName from MCInstPrinter implementations in favor of ↵Craig Topper2012-04-022-50/+0
| | | | | | using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations. llvm-svn: 153863
* Use SequenceToOffsetTable to generate instruction name table for AsmWriter.Craig Topper2012-04-021-25/+27
| | | | llvm-svn: 153857
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