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* AsmMatchers: Use unique_ptr to manage ownership of MCParsedAsmOperandDavid Blaikie2014-06-081-24/+23
| | | | | | | | | | | | I saw at least a memory leak or two from inspection (on probably untested error paths) and r206991, which was the original inspiration for this change. I ran this idea by Jim Grosbach a few weeks ago & he was OK with it. Since it's a basically mechanical patch that seemed sufficient - usual post-commit review, revert, etc, as needed. llvm-svn: 210427
* Teach the table generated emitPseudoExpansionLowering function to not emit a ↵Aaron Ballman2014-05-231-61/+65
| | | | | | switch statement containing only a default statement (and no cases). Updated some of the code to use range-based for loops as well. No functional changes. llvm-svn: 209521
* ARM64: separate load/store operands to simplify assemblerTim Northover2014-05-221-3/+3
| | | | | | | | | | | | | | | | | | | This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
* [asm matcher] Fix incorrect assertion when there are exactly 32 ↵Daniel Sanders2014-05-211-13/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | SubtargetFeatures Summary: The minimal type needs to hold a value of '1ULL << 31' but getMinimalTypeForRange() is called with a value of '1ULL << 32'. This patch will also reduce the size of the matcher table when there are 8 or 16 SubtargetFeatures. Also added a dump of the SubtargetFeatures to the -debug output and corrected getMinimalTypeInRange() to consider 0xffffffffull to be a 32-bit value. The testcase is that no existing code is broken and that LLVM still successfully compiles after adding MIPS64r6 CodeGen support. Reviewers: rafael Reviewed By: rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3787 llvm-svn: 209288
* [modules] Add module maps for LLVM. These are not quite ready for prime-timeRichard Smith2014-05-211-0/+4
| | | | | | | yet, but only a few more Clang patches need to land. (I have 'ninja check' passing locally.) llvm-svn: 209269
* Clean up language and grammar.Eric Christopher2014-05-201-2/+2
| | | | | | | Based on a patch by jfcaron3@gmail.com! PR19806 llvm-svn: 209216
* TableGen: permit non-leaf ComplexPattern usesTim Northover2014-05-203-56/+165
| | | | | | | | | | | | | | | | | | This allows the results of a ComplexPattern check to be distributed to separate named Operands, instead of the current system where all results must apply (and match perfectly) with a single Operand. For example, if "some_addrmode" is a ComplexPattern producing two results, you can write: def : Pat<(load (some_addrmode GPR64:$base, imm:$offset)), (INST GPR64:$base, imm:$offset)>; This should allow neater instruction definitions in TableGen that don't put all possible aspects of addressing into a single operand, but are still usable with relatively simple C++ CodeGen idioms. llvm-svn: 209206
* TableGen: convert InstAlias's Emit bit to an int.Tim Northover2014-05-201-13/+31
| | | | | | | | | | | | | When multiple aliases overlap, the correct string to print can often be determined purely by considering the InstAlias declarations in some particular order. This allows the user to specify that order manually when desired, without resorting to hacking around with the default lexicographical order on Record instantiation, which is error-prone and ugly. I was also mistaken about "add w2, w3, w4" being the same as "add w2, w3, w4, uxtw". That's only true if Rn is the stack pointer. llvm-svn: 209199
* Fix typos.Eric Christopher2014-05-191-2/+1
| | | | llvm-svn: 209164
* TableGen: fix operand counting for aliasesTim Northover2014-05-161-32/+7
| | | | | | | | | | | | | | | | | | | | | TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" llvm-svn: 208969
* TableGen: use correct MIOperand when printing aliasesTim Northover2014-05-153-9/+36
| | | | | | | | | | | | | | Previously, TableGen assumed that every aliased operand consumed precisely 1 MachineInstr slot (this was reasonable because until a couple of days ago, nothing more complicated was eligible for printing). This allows a couple more ARM64 aliases to print so we can remove the special code. On the X86 side, I've gone for explicit AT&T size specifiers as the default, so turned off a few of the aliases that would have just started printing. llvm-svn: 208880
* TableGen/ARM64: print aliases even if they have syntax variants.Tim Northover2014-05-154-35/+54
| | | | | | | To get at least one use of the change (and some actual tests) in with its commit, I've enabled the AArch64 & ARM64 NEON mov aliases. llvm-svn: 208867
* Fix typosAlp Toker2014-05-151-1/+1
| | | | llvm-svn: 208839
* Teach the table generator to not generate switch statements containing only ↵Aaron Ballman2014-05-131-12/+15
| | | | | | | | a default label with no cases. This solves some warnings with MSVC. No functional changes intended. llvm-svn: 208694
* TableGen: strengthen assertTim Northover2014-05-131-1/+1
| | | | llvm-svn: 208679
* Fix gcc -Wparentheses warning.Jay Foad2014-05-131-1/+2
| | | | llvm-svn: 208675
* TableGen: use PrintMethods to print more aliasesTim Northover2014-05-121-18/+79
| | | | llvm-svn: 208607
* Move late partial-unrolling thresholds into the processor definitionsHal Finkel2014-05-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | The old method used by X86TTI to determine partial-unrolling thresholds was messy (because it worked by testing target features), and also would not correctly identify the target CPU if certain target features were disabled. After some discussions on IRC with Chandler et al., it was decided that the processor scheduling models were the right containers for this information (because it is often tied to special uop dispatch-buffer sizes). This does represent a small functionality change: - For generic x86-64 (which uses the SB model and, thus, will get some unrolling). - For AMD cores (because they still currently use the SB scheduling model) - For Haswell (based on benchmarking by Louis Gerbarg, it was decided to bump the default threshold to 50; we're working on a test case for this). Otherwise, nothing has changed for any other targets. The logic, however, has been moved into BasicTTI, so other targets may now also opt-in to this functionality simply by setting LoopMicroOpBufferSize in their processor model definitions. llvm-svn: 208289
* Debug.h already includes raw_ostream.h, no need to include it again.Eric Christopher2014-05-071-1/+0
| | | | llvm-svn: 208235
* ArrayRef-ize the Feature and Processor tables for SubtargetFeatures.Eric Christopher2014-05-061-12/+12
| | | | | | | | This removes arguments passed everywhere and allows the use of standard iteration over lists. Should be no functional change. llvm-svn: 208127
* AArch64/ARM64: implement diagnosis of unpredictable loads & storesTim Northover2014-05-061-4/+7
| | | | llvm-svn: 208091
* [C++11] Use 'nullptr' in tablegen output files.Craig Topper2014-04-303-11/+11
| | | | llvm-svn: 207611
* raw_ostream: Forward declare OpenFlags and include FileSystem.h only where ↵Benjamin Kramer2014-04-291-0/+1
| | | | | | necessary. llvm-svn: 207593
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-227-12/+14
| | | | | | definition below all of the header #include lines, TableGen edition. llvm-svn: 206846
* Simplify DFAPacketizerEmitter State copy/move semantics to use compiler ↵David Blaikie2014-04-211-6/+0
| | | | | | defaults. llvm-svn: 206824
* [Modules] Make Support/Debug.h modular. This requires it to not changeChandler Carruth2014-04-214-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | behavior based on other files defining DEBUG_TYPE, which means it cannot define DEBUG_TYPE at all. This is actually better IMO as it forces folks to define relevant DEBUG_TYPEs for their files. However, it requires all files that currently use DEBUG(...) to define a DEBUG_TYPE if they don't already. I've updated all such files in LLVM and will do the same for other upstream projects. This still leaves one important change in how LLVM uses the DEBUG_TYPE macro going forward: we need to only define the macro *after* header files have been #include-ed. Previously, this wasn't possible because Debug.h required the macro to be pre-defined. This commit removes that. By defining DEBUG_TYPE after the includes two things are fixed: - Header files that need to provide a DEBUG_TYPE for some inline code can do so by defining the macro before their inline code and undef-ing it afterward so the macro does not escape. - We no longer have rampant ODR violations due to including headers with different DEBUG_TYPE definitions. This may be mostly an academic violation today, but with modules these types of violations are easy to check for and potentially very relevant. Where necessary to suppor headers with DEBUG_TYPE, I have moved the definitions below the includes in this commit. I plan to move the rest of the DEBUG_TYPE macros in LLVM in subsequent commits; this one is big enough. The comments in Debug.h, which were hilariously out of date already, have been updated to reflect the recommended practice going forward. llvm-svn: 206822
* Fix builds that use an stl missing std::set::emplaceDavid Blaikie2014-04-211-1/+1
| | | | llvm-svn: 206821
* Store State objects by value in TableGen's DFAPacketizerEmitterDavid Blaikie2014-04-211-34/+30
| | | | | | | | | Removes some extra manual dynamic memory allocation/management. It does get a bit quirky having to make State's members mutable and pointers/references to const rather than non-const, but that's a necessary workaround to dealing with the std::set elements. llvm-svn: 206807
* Use Regex objects by value (rather than 'new'ed) in CodeGenSchedule.David Blaikie2014-04-211-6/+4
| | | | llvm-svn: 206800
* More C++ification.Richard Smith2014-04-201-1/+2
| | | | llvm-svn: 206722
* Don't provide two different definitions of ModRMDecision, OpcodeDecision, ↵Richard Smith2014-04-201-6/+23
| | | | | | and ContextDecision in different source files (depending on #define magic). llvm-svn: 206720
* Don't define llvm::X86Disassembler::InstructionSpecifier in different ways inRichard Smith2014-04-201-11/+12
| | | | | | different source files. llvm-svn: 206719
* Fix redefinition of default argument, found by modules build. It's notRichard Smith2014-04-201-5/+4
| | | | | | | | | entirely clear whether this should be valid with modules enabled, but the fixed code is cleaner regardless. Also fix a TU-local type that accidentally had external linkage. llvm-svn: 206714
* c++11: Tidy up tblgen w/ range loops.Jim Grosbach2014-04-181-62/+53
| | | | | | IntrInfoEmitter cleanup. llvm-svn: 206553
* iterator access to scheduling classesJim Grosbach2014-04-181-0/+22
| | | | llvm-svn: 206552
* iterator_range accessor for CodeGenTarget instruction list.Jim Grosbach2014-04-182-1/+3
| | | | llvm-svn: 206551
* iterator based accessors for CodeGenInstruction operand list.Jim Grosbach2014-04-181-0/+7
| | | | llvm-svn: 206550
* remove some dead codeNuno Lopes2014-04-173-22/+0
| | | | | | | | | | | | | | | lib/Analysis/IPA/InlineCost.cpp | 18 ------------------ lib/Analysis/RegionPass.cpp | 1 - lib/Analysis/TypeBasedAliasAnalysis.cpp | 1 - lib/Transforms/Scalar/LoopUnswitch.cpp | 21 --------------------- lib/Transforms/Utils/LCSSA.cpp | 2 -- lib/Transforms/Utils/LoopSimplify.cpp | 6 ------ utils/TableGen/AsmWriterEmitter.cpp | 13 ------------- utils/TableGen/DFAPacketizerEmitter.cpp | 7 ------- utils/TableGen/IntrinsicEmitter.cpp | 2 -- 9 files changed, 71 deletions(-) llvm-svn: 206506
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-164-16/+19
| | | | | | instead of comparing to nullptr. llvm-svn: 206356
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-1518-92/+92
| | | | | | instead of comparing to nullptr. llvm-svn: 206254
* Retire llvm::array_endof in favor of non-member std::end.Benjamin Kramer2014-04-121-4/+4
| | | | | | While there make array_lengthof constexpr if we have support for it. llvm-svn: 206112
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-042-7/+7
| | | | llvm-svn: 205610
* tblgen: Twinify PrintFatalError.Benjamin Kramer2014-03-296-34/+38
| | | | | | No functionality change. llvm-svn: 205110
* TableGen: don't save a StringRef to a local std::string.Tim Northover2014-03-291-2/+2
| | | | | | This caused a failure in some Windows builds. llvm-svn: 205109
* TableGen: avoid dereferencing nullptr variableTim Northover2014-03-291-6/+10
| | | | | | | ARM64 ended up reaching odder parts of TableGen alias generation than current backends and caused a segfault. llvm-svn: 205089
* Intrinsics: add LLVMHalfElementsVectorType constraintTim Northover2014-03-291-1/+4
| | | | | | | | | | This is like the LLVMMatchType, except the verifier checks that the second argument is a vector with the same base type and half the number of elements. This will be used by the ARM64 backend. llvm-svn: 205079
* Intrinsics: expand semantics of LLVMExtendedVectorType (& trunc)Tim Northover2014-03-282-10/+10
| | | | | | | | | | | | These are used in the ARM backends to aid type-checking on patterns involving intrinsics. By making sure one argument is an extended/truncated version of another. However, there's no reason to limit them to just vectors types. For example AArch64 has the instruction "uqshrn sD, dN, #imm" which would naturally use an intrinsic taking an i64 and returning an i32. llvm-svn: 205003
* remove a bunch of unused private methodsNuno Lopes2014-03-231-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | found with a smarter version of -Wunused-member-function that I'm playwing with. Appologies in advance if I removed someone's WIP code. include/llvm/CodeGen/MachineSSAUpdater.h | 1 include/llvm/IR/DebugInfo.h | 3 lib/CodeGen/MachineSSAUpdater.cpp | 10 -- lib/CodeGen/PostRASchedulerList.cpp | 1 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 10 -- lib/IR/DebugInfo.cpp | 12 -- lib/MC/MCAsmStreamer.cpp | 2 lib/Support/YAMLParser.cpp | 39 --------- lib/TableGen/TGParser.cpp | 16 --- lib/TableGen/TGParser.h | 1 lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 9 -- lib/Target/ARM/ARMCodeEmitter.cpp | 12 -- lib/Target/ARM/ARMFastISel.cpp | 84 -------------------- lib/Target/Mips/MipsCodeEmitter.cpp | 11 -- lib/Target/Mips/MipsConstantIslandPass.cpp | 12 -- lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 21 ----- lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 2 lib/Target/PowerPC/PPCFastISel.cpp | 1 lib/Transforms/Instrumentation/AddressSanitizer.cpp | 2 lib/Transforms/Instrumentation/BoundsChecking.cpp | 2 lib/Transforms/Instrumentation/MemorySanitizer.cpp | 1 lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 8 - lib/Transforms/Scalar/SCCP.cpp | 1 utils/TableGen/CodeEmitterGen.cpp | 2 24 files changed, 2 insertions(+), 261 deletions(-) llvm-svn: 204560
* [TableGen] Don't assert, produce an error, when an instruction has too few ↵Hal Finkel2014-03-221-1/+12
| | | | | | | | | | | operands When an instruction's operand list does not have a sufficient number of operands to match with all of the variables that contribute to its encoding, instead of asserting inside a call to getSubOperandNumber, produce an informative error. llvm-svn: 204542
* Expose "noduplicate" attribute as a property for intrinsics.Eli Bendersky2014-03-183-1/+17
| | | | | | | | | | | | The "noduplicate" function attribute exists to prevent certain optimizations from duplicating calls to the function. This is important on platforms where certain function call duplications are unsafe (for example execution barriers for CUDA and OpenCL). This patch makes it possible to specify intrinsics as "noduplicate" and translates that to the appropriate function attribute. llvm-svn: 204200
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